参数资料
| 型号： | ISL6328IRZ |
| 厂商： | Intersil |
| 文件页数： | 18/33页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR PWM SYNC BUCK DL 48QFN |
| 标准包装： | 50 |
| 应用： | 控制器，AMD SVI |
| 输入电压： | 5 V ~ 12 V |
| 输出数： | 2 |
| 输出电压： | 0.0125 V ~ 1.55 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | * |
| 封装/外壳： | * |
| 供应商设备封装： | * |
| 包装： | * |
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ISL6328
described previously. The output voltage will then be stepped up
or down to the appropriate VID level. Finally, the ISL6328 will
then re-enter Power Savings Mode.
While in Power Savings Mode, the ISL6328 implements two
features that effectively enhance the efficiency of the regulator
upper specification limit, a larger negative spike can be sustained
without crossing the lower limit. By adding a well controlled output
impedance, the output voltage under load can effectively be level
shifted down so that a larger positive spike can be sustained without
crossing the upper specification limit.
even more. These features are Diode Emulation and Gate Voltage
Optimization.
DIODE EMULATION
While in Power Savings Mode, the active phases will behave as if they
are in a standard buck configuration. To accomplish this, the lower
EXTERNAL CIRCUIT
COMP
ISL6328 INTERNAL CIRCUIT
DROOP
CONTROL
MOSFET is turned on only while there is current flowing to the load. This
behavior emulates the diode in a standard buck. The conduction loss
across the R DS (on) of the MOSFET, however, is much less than a diode,
resulting in a measurable power savings.
GATE VOLTAGE OPTIMIZATION
C C
R C
FB
-
I AVG
I OFS
V COMP
While in Power Savings Mode, the gate drive voltage for the lower
MOSFETs of the active phases is reduced from the nominal 12V
+
ERROR
AMPLIFIER
that is utilized in Normal mode to 5.75V. Lowering the gate drive
voltage can have an appreciable effect on the efficiency of the
converter.
R FB
+
-
(V DROOP + V OFS )
2k
In order to utilize 5V gate drive at all times, 5V should be tied to
the PVCC pin and the GVOT pin should be shorted to the PVCC
pin. This configuration will allow for 5V gate drive in all modes of
operation.
+
V OUT
-
VSEN
RGND
∑
VID
DAC
Voltage Regulation
The integrating compensation network shown in Figure 8 insures
that the steady-state error in the output voltage is limited only to
the error in the reference voltage and offset errors in the OFS
current source, remote-sense and error amplifiers. Intersil
specifies the guaranteed tolerance of the ISL6328 to include the
combined tolerances of each of these elements.
FIGURE 8. OUTPUT VOLTAGE AND LOAD-LINE REGULATION WITH
OFFSET ADJUSTMENT
As shown in Figure 8, with droop enabled, the average current of
all active channels, I AVG , flows from FB through a load-line
regulation resistor R FB . The resulting voltage drop across R FB is
proportional to the output current, effectively creating an output
The output of the error amplifier, V COMP , is used by the
modulator to generate the PWM signals. The PWM signals
voltage droop with a steady-state value defined as:
V DROOP = I AVG ? R FB
(EQ. 16)
V OUT = V REF – V OFS – V DROOP
V OUT = V REF – V OFS – ? ----------- ? --------------- ? K ? R FB ?
control the timing of the Internal MOSFET drivers and regulate
the converter output so that the voltage at FB is equal to the
voltage at REF. This will regulate the output voltage to be equal to
Equation 15. The internal and external circuitry that controls
voltage regulation is illustrated in Figure 8.
(EQ. 15)
The ISL6328 incorporates differential remote-sense amplification in
the feedback path. The differential sensing removes the voltage
error encountered when measuring the output voltage relative to the
controller ground reference point resulting in a more accurate
means of sensing output voltage.
Load-Line (Droop) Regulation
By adding a well controlled output impedance, the output voltage
can effectively be level shifted in a direction which works to
achieve a cost-effective solution can help to reduce the output-
voltage spike that results from fast load-current demand
changes.
The magnitude of the spike is dictated by the ESR and ESL of the output
capacitors selected. By positioning the no-load voltage level near the
18
The regulated output voltage is reduced by the droop voltage
V DROOP . The output voltage as a function of load current is
shown in Equation 17.
? I OUT DCR ? (EQ. 17)
? N R ISEN ?
In Equation 17, V REF is the reference voltage, V OFS is the
programmed offset voltage, I OUT is the total output current of the
converter, K is the DC gain of the RC filter across the inductor (K
is defined in Equation 8), N is the number of active channels, and
DCR is the distributed inductor impedance value.
Droop Control
The DRPCTRL (Droop Control) pin is used to enable and/or
disable load line regulation on both the Core and Northbridge
regulators. The pin is also used to set the number of phases in
Power Savings Mode (PSI) mode. A single resistor tied from the
DRPCTRL pin to either GND or VCC will program the ISL6328 to
either enable or disable droop on both Core and Northbridge
simultaneously.
FN7621.1
June 7, 2011
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ISL6328IRZ-T | 功能描述:IC CTRLR PWM SYNC BUCK DL 48QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 标准包装:2,000 系列:- 应用:控制器，DSP 输入电压:4.5 V ~ 25 V 输出数:2 输出电压:最低可调至 1.2V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:30-TFSOP（0.173"，4.40mm 宽） 供应商设备封装:30-TSSOP 包装:带卷 (TR) |
| ISL6329CRZ | 功能描述:电压模式 PWM 控制器 6+1 PHS DL PWM CONTRLR FOR CORE RoHS:否 制造商:Texas Instruments 输出端数量:1 拓扑结构:Buck 输出电压:34 V 输出电流: 开关频率: 工作电源电压:4.5 V to 5.5 V 电源电流:600 uA 最大工作温度:+ 125 C 最小工作温度:- 40 C 封装 / 箱体:WSON-8 封装:Reel |
| ISL6329CRZ-T | 功能描述:电压模式 PWM 控制器 6+1 PHS DL PWM CONTRLR FOR CORE RoHS:否 制造商:Texas Instruments 输出端数量:1 拓扑结构:Buck 输出电压:34 V 输出电流: 开关频率: 工作电源电压:4.5 V to 5.5 V 电源电流:600 uA 最大工作温度:+ 125 C 最小工作温度:- 40 C 封装 / 箱体:WSON-8 封装:Reel |
| ISL6329EVAL1Z | 制造商:Intersil Corporation 功能描述:ISL6329 EVALUATION BOARD - 60 LEAD - QFN - ROHS COMPLIANT - Bulk |
| ISL6329IRZ | 功能描述:电压模式 PWM 控制器 6+1 PHS DL PWM CONTRLR FOR CORE RoHS:否 制造商:Texas Instruments 输出端数量:1 拓扑结构:Buck 输出电压:34 V 输出电流: 开关频率: 工作电源电压:4.5 V to 5.5 V 电源电流:600 uA 最大工作温度:+ 125 C 最小工作温度:- 40 C 封装 / 箱体:WSON-8 封装:Reel |
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