参数资料
型号: ISL6336BCRZ
厂商: Intersil
文件页数: 13/31页
文件大小: 0K
描述: IC CTRLR PWM SYNC BUCK 48-QFN
标准包装: 43
应用: 控制器,Intel VR11.1
输入电压: 3 V ~ 12 V
输出数: 1
输出电压: 0.5 V ~ 1.6 V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 48-VFQFN 裸露焊盘
供应商设备封装: 48-QFN(7x7)
包装: 管件
产品目录页面: 1248 (CN2011-ZH PDF)
ISL6336B
frequency set by the resistor between the FS pin and
ground. The PWM signals command the MOSFET drivers to
turn on/off the channel MOSFETs.
In the default 6-phase operation, the PWM2 pulse happens
1/6 of a cycle after PWM1, the PWM3 pulse happens 1/6 of
a cycle after PWM2, etc.
The ISL6336B works in a 1- to 6-phase configuration.
Connecting the PWM6 pin to VCC selects 5-phase operation
and the pulse times are spaced in 1/5 cycle increments.
Connecting the PWM5 pin to VCC selects 4-phase operation
and the pulse times are spaced in 1/4 cycle increments, etc.
When PSI# is pulled LOW, indicating low power operation of
the processor, the controller reduces the number of active
phases and operates 1- or 2-phases to improve efficiency
based on the logic in Table 2. Table 1 shows which phases
will be active when PSI# = 0 based on the phase count of the
application. For example, If operating in a 6-phase
configuration, phase 1 will be active if dropping to 1-phase
and phases 1 and 4 will be active if dropping to 2-phases.
TABLE 1. NUMBER OF ACTIVE PHASES AND PWM FIRING
SEQUENCE
PHASE
both the dropped phase(s) and active phases as PSI# is
asserted and de-asserted. In Table 2, ‘VCC’ means that the
resistor is connected from the respective pin to VCC and ‘GND’
means the resistor is connected from the respective pin to
GND.
When PSI# goes LOW, the dropped phase’s PWM signal is
forced LOW for a minimum time, 200ns typically, and then is
driven to 1/2*VCC while the remaining active phase PWM(s)
sends out a repetitive 3-level PWM pattern that the
dedicated VR11.1 drivers (ISL6622/ISL6620) can decode
and then enter diode emulation mode.
During soft-start or overcurrent hiccup mode all phases will be
operating despite the state of the PSI# pin. Once VR_RDY is
asserted the state of the PSI# pin is considered. In addition, a
LOW signal at the H_CPURST_N pin disables PSI# mode.
The state of the PSI# signal will not be recognized as LOW
until approximately 45ms (see “Electrical Specifications” table
on page 7 for the delay time range) after H_CPURST_N
returns to a logic HIGH state. The LOW and HIGH thresholds
are 0.4V and 0.8V respectively. A logic LOW can be obtained
by pulling this pin to ground with a suitable small signal
device, while a logic HIGH can be obtained by leaving the pin
open or connecting to the processor VTT (~1.1V) via a
SEQUENCE
ACTIVE
suitable pull-up. If the PSI# lockout is not desired at any time
PHASE
COUNT
6-Phase
5-Phase
4-Phase
3-Phase
2-Phase
1-Phase
NORMAL
OPERATION
1-2-3-4-5-6
1-2-3-4-5
1 - 2 - 3- 4
1-2-3
1-2
1
PWM/VCC
-
PWM6 = VCC
PWM5:6 = VCC
PWM4:6 = VCC
PWM3:6 = VCC
PWM2:6 = VCC
PHASES
PSI# = 0
Phase 1/4
Phase 1/3
Phase 1/3
Phase 1/2
Phase 1/2
-
during the operation of the IC, then connect H_CPURST_N to
VCC.
This unique function eliminates the required external
circuitry for proper PSI# operation of Intel’s Eaglelake
chipset platforms, reducing cost and PCB space. This
function can be disabled making the ISL6336B compatible
with the ISL6336 for other platform implementations.
A high PSI# input signal will force the controller back into
CCM normal operation and all phases will be activated to
TABLE 2. PHASE DROPPING BEHAVIOR
sustain a heavy load transient and to increase efficiency at
higher loads.
CONFIGURATION
Non-CI or (N - 1) - CI Drops to 1-Phase
FS SS
PSI# RESISTOR RESISTOR
0 GND GND
While the controller is operational (VCC above POR,
EN_VTT and EN_PWR are both high, valid VID inputs), it
can pull the PWM pins to ~40% of VCC (~2V for 5V VCC
Non-CI or (N - 2) - CI Drops to 2-Phase
2-Phase CI Drops to 1-Phase
2-Phase CI Drops to 2-Phase
Normal PWM CCM Mode
0
0
0
1
GND
VCC
VCC
x
VCC
GND
VCC
x
bias) during various stages, such as soft-start delay, phase
shedding operation, or fault conditions (OC or OV events).
The matching driver's internal PWM resistor divider can
further raise the PWM potential, but not lower it below the
level set by the controller IC. Therefore, the controller's
The SS and FS pins are used to program the controllers PWM
behavior in configurations using standard inductors, 2-phase
coupled inductors or (N - 1)/(N - 2)-phase coupled inductors
when PSI# goes LOW. Two-phase coupled inductors refer to
inductor structures that magnetically couple 2-phases together.
(N - 1) and (N - 2) coupled inductors refer to structures that
couple all phases together except for the 1- or 2-phases that
remain active in PSI# mode. N refers to the programmed
number of active phases in normal operation, PSI# = 1 (See
Table 1). Each case yields different PWM output behavior on
13
PWM outputs are directly compatible with Intersil drivers that
require 5V PWM signal amplitudes. Drivers requiring 3.3V
PWM signal amplitudes are generally incompatible.
Switching Frequency
The switching frequency is determined by the selection of
the frequency-setting resistor, R T , which is connected from
FS pin to GND or VCC (see “Typical Application - 5-Phase
FN6696.2
August 31, 2010
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