参数资料
| 型号： | ISL6423ERZ-T |
| 厂商： | Intersil |
| 文件页数： | 11/16页 |
| 文件大小： | 0K |
| 描述： | IC VREG SGL LNB W/I2C 24-QFN |
| 标准包装： | 6,000 |
| 应用： | 转换器，卫星信号接收机顶盒设计 |
| 输入电压： | 8 V ~ 14 V |
| 输出数： | 1 |
| 输出电压： | 13.3 V ~ 18.3 V，14.3 V ~ 19.3 V |
| 工作温度： | -20°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-VFQFN 裸露焊盘 |
| 供应商设备封装： | 24-QFN 裸露焊盘（4x4） |
| 包装： | 带卷 (TR) |
ISL6423
Byte Format
Every byte put on the SDA line must be eight bits long. The
number of bytes that can be transmitted per transfer is
unrestricted. Each byte has to be followed by an
acknowledge bit. Data is transferred with the most significant
bit first (MSB).
Acknowledge
The master (microprocessor) puts a resistive HIGH level on
the SDA line during the acknowledge clock pulse (Figure 6).
The peripheral that acknowledges has to pull-down (LOW)
the SDA line during the acknowledge clock pulse, so that the
SDA line is stable LOW during this clock pulse. (Of course,
set-up and hold times must also be taken into account.)
ISL6423 Software Description
Interface Protocol
The interface protocol is comprised of the following, as
shown below in Table 2:
? A start condition (S)
? A chip address byte (MSB on left; the LSB bit determines
read (1) or write (0) transmission) (the assigned I 2 C slave
address for the ISL6423 is 0001 0 XX X)
? A sequence of data (1 byte + Acknowledge)
? A stop condition (P)
TABLE 2. INTERFACE PROTOCOL
The peripheral which has been addressed has to generate
S 0
0
0
1
0
A1
A0 R/W ACK
Data (8 bits)
ACK P
an acknowledge after the reception of each byte, otherwise
the SDA line remains at the HIGH level during the ninth
clock pulse time. In this case, the master transmitter can
generate the STOP information in order to abort the transfer.
The ISL6423 will not generate the acknowledge if the
System Register Format
? R, W = Read and Write bit
? R = Read-only bit
All bits reset to 0 at Power-On
POWER OK signal from the UVLO is LOW.
TABLE 3. STATUS REGISTER (SR1)
SCL
R, W
R, W
R, W
R
R
R
R
R
1
2
8
9
SR1H
SR1M
SR1L
OTF
CABF
OUVF
OLF
BCF
SDA
TABLE 4. TONE REGISTER (SR2)
MSB
START
ACKNOWLEDGE
FROM SLAVE
R, W
SR2H
R, W
SR2M
R, W
SR2L
R, W
ENT
R, W
MSEL
R, W
TTH
R, W
X
R, W
X
FIGURE 6. ACKNOWLEDGE ON THE I 2 C BUS
TABLE 5. COMMAND REGISTER (SR3)
Transmission Without Acknowledge
R, W
R, W
R, W
R, W
R, W
R, W
R, W
R, W
Avoiding detection of the acknowledgement, the
SR3H SR3M SR3L
DCL
VSPEN
X
ISELH ISELL
microprocessor can use a simpler transmission; it waits one
clock without checking the slave acknowledging, and sends
TABLE 6. CONTROL REGISTER (SR4)
the new data.
R, W
R, W
R, W
R, W
R, W
R, W
R, W
R, W
This approach, though, is less protected from error and
SR4H SR4M SR4L
EN
VTOP
VBOT
decreases the noise immunity.
Transmitted Data ( I 2 C bus WRITE mode)
When the R/W bit in the chip is set to 0, the main
microprocessor can write on the system registers (SR2 thru
SR4) of the ISL6423 via I 2 C bus. These will be written by the
microprocessor as shown below. The spare bits of registers
can be used for other functions.
11
FN9191.2
December 5, 2008
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