参数资料
| 型号： | ISL6423ERZ-T |
| 厂商： | Intersil |
| 文件页数： | 16/16页 |
| 文件大小： | 0K |
| 描述： | IC VREG SGL LNB W/I2C 24-QFN |
| 标准包装： | 6,000 |
| 应用： | 转换器，卫星信号接收机顶盒设计 |
| 输入电压： | 8 V ~ 14 V |
| 输出数： | 1 |
| 输出电压： | 13.3 V ~ 18.3 V，14.3 V ~ 19.3 V |
| 工作温度： | -20°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-VFQFN 裸露焊盘 |
| 供应商设备封装： | 24-QFN 裸露焊盘（4x4） |
| 包装： | 带卷 (TR) |
ISL6423
Thin Shrink Small Outline Exposed Pad Plastic Packages (EPTSSOP)
N
M28.173B
INDEX
AREA
E1
E
0.25(0.010) M
B M
28 LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE
INCHES MILLIMETERS
-B-
GAUGE
PLANE
SYMBOL
A
MIN
-
MAX
0.047
MIN
-
MAX
1.20
NOTES
-
1
2
3
A1
0.002
0.006
0.05
0.15
-
TOP VIEW
0.05(0.002)
-A-
D
SEATING PLANE
A
0.25
0.010
L
A2
b
c
D
0.031
0.0075
0.0035
0.378
0.051
0.0118
0.0079
0.386
0.80
0.19
0.09
9.60
1.05
0.30
0.20
9.80
-
9
-
3
-C-
α
A2
E1
e
0.169 0.177
0.026 BSC
4.30 4.50
0.65 BSC
4
-
e
A1
c
E
0.246
0.256
6.25
6.50
-
b
0.10(0.004) M
C A M
B S
0.10(0.004)
L
N
α
0.0177
0°
28
0.0295
8°
0.45
0°
28
0.75
8°
6
7
-
P
-
0.138
-
5.50
11
1
2
3
P1
-
0.118
-
3.0
11
Rev. 0 6/05
P1
NOTES:
1. These package dimensions are within allowable dimensions of
JEDEC MO-153-AET, Issue E.
N
P
BOTTOM VIEW
2. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.15mm (0.006
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08mm (0.003 inch) total in excess
of “b” dimension at maximum material condition. Minimum space
between protrusion and adjacent lead is 0.07mm (0.0027 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimen-
sions are not necessarily exact. (Angles in degrees)
11. Dimensions “P” and “P1” are thermal and/or electrical enhanced
variations. Values shown are maximum size of exposed pad
within lead count and body size.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
16
FN9191.2
December 5, 2008
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