参数资料
| 型号： | ISL6423ERZ-T |
| 厂商： | Intersil |
| 文件页数： | 13/16页 |
| 文件大小： | 0K |
| 描述： | IC VREG SGL LNB W/I2C 24-QFN |
| 标准包装： | 6,000 |
| 应用： | 转换器，卫星信号接收机顶盒设计 |
| 输入电压： | 8 V ~ 14 V |
| 输出数： | 1 |
| 输出电压： | 13.3 V ~ 18.3 V，14.3 V ~ 19.3 V |
| 工作温度： | -20°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-VFQFN 裸露焊盘 |
| 供应商设备封装： | 24-QFN 裸露焊盘（4x4） |
| 包装： | 带卷 (TR) |
ISL6423
TABLE 10. CONTROL REGISTER SR4 CONFIGURATION
SR4H
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SR4M
1
1
1
1
1
1
1
1
1
1
1
1
1
1
SR4L
1
1
1
1
1
1
1
1
1
1
1
1
1
1
EN
1
1
1
1
1
1
1
1
1
1
1
1
1
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
VTOP
0
0
0
1
1
0
0
1
1
0
0
1
1
X
VBOT
0
0
1
0
1
0
1
0
1
0
1
0
1
X
FUNCTION
SR4 is selected
VSPEN = SELVTOP = 0, Vout1 = 13V, Vboost1 = 13V + Vdrop
VSPEN = SELVTOP = 0, Vout1 = 14V, Vboost1 = 14V + Vdrop
VSPEN = SELVTOP = 0, Vout1 = 13V, Vboost1 = 13V + Vdrop
VSPEN = SELVTOP = 0, Vout1 = 14V, Vboost1 = 14V + Vdrop
VSPEN = 0, SELVTOP = 1, Vout1 = 18V, Vboost1 = 18V + Vdrop
VSPEN = 0, SELVTOP = 1, Vout1 = 18V, Vboost1 = 18V + Vdrop
VSPEN = 0, SELVTOP = 1, Vout1 = 19V, Vboost1 = 19V + Vdrop
VSPEN = 0, SELVTOP = 1, Vout1 = 19V, Vboost1 = 19V + Vdrop
VSPEN = 1, SELVTOP = X Vout1 = 13V, Vboost1 = 13V + Vdrop
VSPEN = 1, SELVTOP = X Vout1 = 14V, Vboost1 = 14V + Vdrop
VSPEN = 1, SELVTOP = X Vout1 = 18V, Vboost1 = 18V + Vdrop
VSPEN = 1, SELVTOP = X Vout1 = 19V, Vboost1 = 19V + Vdrop
PWM and Linear for channel 1 disabled
NOTE: X indicates “Read Only” and is a “Don’t Care” for the Write mode.
Received Data ( I 2 C bus READ MODE)
The ISL6423 can provide to the master a copy of the system
register information via the I 2 C bus in read mode. The read
mode is Master activated by sending the chip address with
R/W bit set to 1. At the following Master generated clock bits,
the ISL6423 issues a byte on the SDA data bus line (MSB
transmitted first).
ADDR0 and ADDR1 Pins
Connecting these pin to GND the chip I 2 C interface address
is 0001000, but, it is possible to choose between four
different addresses by setting these pins to the logic levels
indicated in Table 11.
TABLE 11. ADDRESS PIN CHARACTERISTICS
At the ninth clock bit the MCU master can:
? Acknowledge the reception, starting in this way the
transmission of another byte from the ISL6423.
? Not acknowledge, stopping the read mode
communication.
V ADDR
V ADDR -1 “0001000”
V ADDR -2 “0001001”
V ADDR -3 “0001010”
V ADDR -4 “0001011”
ADDR1
0
0
1
1
ADDR0
0
1
0
1
The read only bits of the register SR1 convey diagnostic
information about the ISL6423, as indicated in the Table 7.
Power–On I 2 C Interface Reset
The I 2 C interface built into the ISL6423 is automatically reset
at power-on. The I 2 C interface block will receive a power OK
logic signal from the UVLO circuit. This signal will go HIGH
when chip power is OK. As long as this signal is LOW, the
interface will not respond to any I 2 C commands and the
system register SR1 thru SR4 are all initialized to zero, thus
keeping the power blocks disabled. Once the VCC rises
above UVLO, the POWER OK signal to the I 2 C is asserted
high, and the I 2 C interface becomes operative and the SR’s
can be configured by the main microprocessor. About
400mV of hysteresis is provided in the UVLO threshold to
avoid false triggering of the power-on reset circuit. (I 2 C
comes up with EN = 0; EN goes HIGH at the same time as
(or later than) all other I 2 C data for that PWM becomes
valid).
13
FN9191.2
December 5, 2008
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