参数资料
| 型号： | ISL6423ERZ-T |
| 厂商： | Intersil |
| 文件页数： | 9/16页 |
| 文件大小： | 0K |
| 描述： | IC VREG SGL LNB W/I2C 24-QFN |
| 标准包装： | 6,000 |
| 应用： | 转换器，卫星信号接收机顶盒设计 |
| 输入电压： | 8 V ~ 14 V |
| 输出数： | 1 |
| 输出电压： | 13.3 V ~ 18.3 V，14.3 V ~ 19.3 V |
| 工作温度： | -20°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-VFQFN 裸露焊盘 |
| 供应商设备封装： | 24-QFN 裸露焊盘（4x4） |
| 包装： | 带卷 (TR) |
ISL6423
Functional Description
The ISL6423 single output voltage regulator makes an ideal
choice for advanced satellite set-top box and personal video
recorder applications. The device utilizes built-in DC/DC step
up converters that, operates from a single supply source
ranging from 8V to 14V, and generates the voltage needed
to enable the linear post-regulator to work with a minimum of
dissipated power. An undervoltage lockout circuit disables
the device when VCC drops below a fixed threshold (7.5V
typical).
DiSEqC Encoding
The internal oscillator is factory-trimmed to provide a tone of
22kHz in accordance with DiSEqC (EUTELSAT) standards.
No further adjustment is required. The tone oscillator can be
controlled either by the I 2 C interface (ENT bit) or by a
dedicated pin (EXTM) that allows immediate DiSEqC data
encoding separately for each LNB. All the functions of this IC
are controlled via the I 2 C bus by writing to the system
registers. The same registers can be read back, and four bits
will report the diagnostic status. The internal oscillator
operates the converters at twenty times the 22k tone
Linear Regulator
The output linear regulator will sink and source current. This
feature allows full modulation capability into capacitive loads
as high as 0.75 μ F. In order to minimize the power dissipation,
the output voltage of the internal step-up converter is adjusted
to allow the linear regulator to work at minimum dropout.
When the device is put in the shutdown mode (EN = LOW),
the PWM power block is disabled. When the regulator blocks
are active (EN = HIGH and VSPEN = LOW), the output can
be controlled via I 2 C logic to be 13V/14V or 18V/19V
(typical) by means of the VTOP and VBOT bits (voltage
select) for remote controlling of non-DiSEqC LNBs.
When the regulator blocks are active (EN = HIGH and
VSPEN = HIGH), the VBOT and SELVTOP pin will control
the output between 13V and 14V and the VTOP and
SELVTOP pin will control the output between 18V and 19V.
Output Timing
The output voltage rise and fall times can be set by an the
external capacitor on the TCAP pin. The output voltage slew
rate for the rise is given by the equation:
SlewRatein -------- = ----------
frequency. The device offers full I 2 C compatibility, and
supports 2.5V, 3.3V or 5V logic, up to an operational speed of
V 270
ms C
(EQ. 1)
400kHz.
If the Tone Enable (ENT) bit is set LOW and the MSEL bits
set LOW through I 2 C, then the EXTM terminal activates the
internal tone signal, modulating the DC output with a
680mV PP typical symmetrical tone waveform. The presence
of this signal usually provides the LNB with information
about the band to be received.
Burst coding of the tone can be accomplished due to the fast
response of the EXTM input and rapid tone response. This
allows implementation of the DiSEqC (EUTELSAT)
protocols.
When the ENT bit is set HIGH, a continuous 22kHz tone is
generated regardless of the EXTM pin logic status for the
regulator channel LNB-A. The ENT bit must be set LOW
when the EXTM pin is used for DiSEqC encoding.
The EXTM accepts an externally modulated tone command
when the MSEL I 2 C bit is set HIGH and ENT is set LOW.
DiSEqC Decoder
TDIN is the input to the tone decoder. It accepts the tone
signal derived from the Vout thru the 10nF decoupling
capacitor. The detector threshold can be set to 200mV
maximum in the receive mode and to 400mV minimum in the
transmit mode by means of the logic presented to the TXT
pin. If tone is detected the open drain pin TDOUT is asserted
low. This enables the tone diagnostics to be performed,
apart from the normal tone detection function.
9
Where C is the TCAP value in nF. For example, a 150nF
TCAP will provide for a slew rate of 1.8V/ms and thus a rise
time of 3.3ms for a 6V transition. The output fall time is faster
by a factor of 3.5.
The maximum value for TCAP would be based on the
maximum transition time allowed in the system application.
Too small a value of the TCAP can cause high peak currents
in the boost circuit. For example, a 10V/ms slew on a 80μF
VSW capacitor with an inductor of 15μH can cause a peak
inductor current of approximately 2.3A.
Current Limiting
Dynamic current limiting block has four thresholds that can
be selected by the ISEL H and ISEL L bits of the SR. Refer
to Table 8 and Table 9 for threshold selection using these
bits. The DCL bit has to be set to low for this mode of
operation. In this mode the overcurrent protection circuit
works dynamically: 23 μ s after an overload is detected, the
output is shutdown for a time t OFF , typically 900ms.
Simultaneously, the OLF bit of the system register is set to
HIGH. After this time has elapsed, the output is resumed for
a time t ON = 20ms. During t ON , the device output will be
current limited to 990mA. At the end of t ON , if the overload
per that set by ISELL and ISELH bits is still detected, the
protection circuit will again cycle through t OFF and t ON . At
the end of a full t ON in which no overload is detected, normal
operation is resumed and the OLF bit is reset to LOW.
Typical t ON + t OFF time is 920ms as determined by an
internal timer. This dynamic operation greatly reduces the
power dissipation in a short circuit condition, while still
ensuring excellent power-on start-up in most conditions.
FN9191.2
December 5, 2008
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