参数资料
| 型号： | ISL6523CBZ-T |
| 厂商： | Intersil |
| 文件页数： | 11/16页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR VRM8.5 PWM DUAL 28-SOIC |
| 标准包装： | 1,000 |
| 应用： | 控制器，Intel VRM8.5 |
| 输入电压： | 5 V ~ 15 V |
| 输出数： | 4 |
| 输出电压： | 多重 |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 28-SOIC W |
| 包装： | 带卷 (TR) |
ISL6523
Figure 10 highlights the voltage-mode control loop for a
synchronous-rectified buck converter. The output voltage
(V OUT ) is regulated to the Reference voltage level. The
reference voltage level is the DAC output voltage (DACOUT) for
PWM1. The error amplifier output (V E/A ) is compared with the
oscillator (OSC) triangular wave to provide a pulse-width
modulated wave with an amplitude of V IN at the PHASE node.
The PWM wave is smoothed by the output filter (L O and C O )..
1. Pick Gain (R2/R1) for desired converter bandwidth
2. Place 1 ST Zero Below Filter’s Double Pole (~75% F LC )
3. Place 2 ND Zero at Filter’s Double Pole
4. Place 1 ST Pole at the ESR Zero
5. Place 2 ND Pole at Half the Switching Frequency
6. Check Gain against Error Amplifier’s Open-Loop Gain
7. Estimate Phase Margin - Repeat if Necessary
OSC
DRIVER
V IN
Compensation Break Frequency Equations
F Z1 = -----------------------------------
F Z2 = -------------------------------------------------------
F P1 = -------------------------------------------------------
2 π × R 2 × ? ---------------------- ?
F P2 = -----------------------------------
? V OSC
PWM
COMP
-
+
DRIVER
L O
PHASE
C O
V OUT
1
2 π × R 2 × C1
1
2 π × ( R1 + R3 ) × C3
1
C1 × C2
? C1 + C2 ?
1
2 π × R 3 × C3
ESR
V E/A
Z FB
-
+
ERROR
AMP
Z IN
REFERENCE
(PARASITIC)
Figure 11 shows an asymptotic plot of the DC-DC converter’s
gain vs. frequency. The actual Modulator Gain has a high gain
peak dependent on the quality factor (Q) of the output filter,
which is not shown in Figure 11. Using the above guidelines
should yield a Compensation Gain similar to the curve plotted.
The open loop error amplifier gain bounds the compensation
DETAILED COMPENSATION COMPONENTS
gain. Check the compensation gain at F P2 with the capabilities
C 1
COMP
C 2
R 2
-
Z FB
FB
C 3
Z IN
R 1
R 3
V OUT
of the error amplifier. The Closed Loop Gain is constructed on
the log-log graph of Figure 11 by adding the Modulator Gain (in
dB) to the Compensation Gain (in dB). This is equivalent to
multiplying the modulator transfer function to the compensation
transfer function and plotting the gain.
OPEN LOOP
F Z1 F Z2 F P1
F P2
ERROR AMP GAIN
100
? V IN ?
ISL6523
+
DACOUT
80
60
20 log ? ------------------ ?
? V P – P ?
FIGURE 10. VOLTAGE-MODE BUCK CONVERTER
COMPENSATION DESIGN
40
20
COMPENSATION
GAIN
20 log ? -------- ?
The modulator transfer function is the small-signal transfer
function of V OUT /V E/A . This function is dominated by a DC
Gain, given by V IN /V OSC , and shaped by the output filter, with
a double pole break frequency at F LC and a zero at F ESR .
0
-20
-40
R2
? R1 ?
MODULATOR
GAIN
F LC
F ESR
CLOSED LOOP
GAIN
Modulator Break Frequency Equations
-60
10
100
1K
10K
100K
1M
10M
F LC = ----------------------------------------
F ESR = -----------------------------------------
1
2 π × L O × C O
1
2 π × ESR × C O
FREQUENCY (Hz)
FIGURE 11. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
The compensation network consists of the error amplifier
(internal to the ISL6523) and the impedance networks Z IN and
Z FB . The goal of the compensation network is to provide a
closed loop transfer function with high 0dB crossing frequency
(f 0dB ) and adequate phase margin. Phase margin is the
difference between the closed loop phase at f 0dB and 180 o .
The equations below relate the compensation network’s poles,
zeros and gain to the components (R1, R2, R3, C1, C2, and
C3) in Figure 10. Use these guidelines for locating the poles
and zeros of the compensation network:
The compensation gain uses external impedance networks
Z FB and Z IN to provide a stable, high bandwidth (BW) overall
loop. A stable control loop has a gain crossing with
-20dB/decade slope and a phase margin greater than
45 degrees. Include worst case component variations when
determining phase margin.
PWM2 Controller Feedback Compensation
To reduce the number of external small-signal components
required by a typical application, the standard PWM
controller is internally stabilized. The only stability criteria
that needs to be met relates the minimum value of the output
11
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ISL6523EVAL1 | 功能描述:EVALUATION BOARD VRM8.5 ISL6523 RoHS:否 类别:编程器，开发系统 >> 评估板 - DC/DC 与 AC/DC（离线）SMPS 系列:- 产品培训模块:Obsolescence Mitigation Program 标准包装:1 系列:True Shutdown™ 主要目的:DC/DC，步升 输出及类型:1，非隔离 功率 - 输出:- 输出电压:- 电流 - 输出:1A 输入电压:2.5 V ~ 5.5 V 稳压器拓扑结构:升压 频率 - 开关:3MHz 板类型:完全填充 已供物品:板 已用 IC / 零件:MAX8969 |
| ISL6524ACB | 功能描述:IC CTRLR VRM8.5 PWM TRPL 28-SOIC RoHS:否 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,000 系列:- 应用:电源，ICERA E400，E450 输入电压:4.1 V ~ 5.5 V 输出数:10 输出电压:可编程 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:42-WFBGA，WLCSP 供应商设备封装:42-WLP 包装:带卷 (TR) |
| ISL6524ACB-T | 功能描述:IC CTRLR VRM8.5 PWM TRPL 28-SOIC RoHS:否 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,000 系列:- 应用:电源，ICERA E400，E450 输入电压:4.1 V ~ 5.5 V 输出数:10 输出电压:可编程 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:42-WFBGA，WLCSP 供应商设备封装:42-WLP 包装:带卷 (TR) |
| ISL6524ACBZ | 功能描述:IC CTRLR VRM8.5 PWM TRPL 28-SOIC RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 标准包装:43 系列:- 应用:控制器，Intel VR11 输入电压:5 V ~ 12 V 输出数:1 输出电压:0.5 V ~ 1.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-VFQFN 裸露焊盘 供应商设备封装:48-QFN（7x7） 包装:管件 |
| ISL6524ACBZA-T | 功能描述:IC CTRLR VRM8.5 PWM TRPL 28-SOIC RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 标准包装:43 系列:- 应用:控制器，Intel VR11 输入电压:5 V ~ 12 V 输出数:1 输出电压:0.5 V ~ 1.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-VFQFN 裸露焊盘 供应商设备封装:48-QFN（7x7） 包装:管件 |
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