参数资料
型号: ISL6523CBZ-T
厂商: Intersil
文件页数: 9/16页
文件大小: 0K
描述: IC CTRLR VRM8.5 PWM DUAL 28-SOIC
标准包装: 1,000
应用: 控制器,Intel VRM8.5
输入电压: 5 V ~ 15 V
输出数: 4
输出电压: 多重
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 28-SOIC(0.295",7.50mm 宽)
供应商设备封装: 28-SOIC W
包装: 带卷 (TR)
ISL6523
3. Determine I PEAK for I PEAK > I OUT(MAX) + ( ? I) / 2,
where ? I is the output inductor ripple current.
For an equation for the ripple current see the section under
TABLE 1. OUT1 OUTPUT VOLTAGE PROGRAM (Continued)
PIN NAME NOMINAL
DACOUT
component guidelines titled ‘Output Inductor Selection’.
VID3
VID2
VID1
VID0
VID25
VOLTAGE
DS
SET
i
D
OVERCURRENT TRIP:
V > V
× rDS ( ON ) > I OCSET × R OCSET
OCSET
R OCSET
V IN = +5V
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
0
1
0
1
1.350
1.375
1.400
1.425
1
1
0
0
0
1.450
OVER-
I OCSET
200 μ A
VCC
V SET +
i D
1
1
1
0
0
1
0
1
1
0
1.475
1.500
CURRENT
DRIVE
UGATE
+
1
0
1
1
1
1.525
V DS
1
0
1
0
0
1.550
OC
+
-
PHASE
1
1
0
0
1
0
0
1
1
0
1.575
1.600
PHASE
IN
DS
PWM
GATE
CONTROL
V = V – V
V OCSET = V IN – V SET
1
1
1
0
0
0
0
0
0
1
0
0
1
0
1
1.625
1.650
1.675
0
1
1
1
0
1.700
FIGURE 8. OVERCURRENT DETECTION
OUT1 Voltage Program
The output voltage of the PWM1 converter is programmed to
discrete levels between 1.050V and 1.825V. This output
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
0
0
1
1
1
0
1
0
1
1.725
1.750
1.775
1.800
1.825
(OUT1) is designed to supply the core voltage of Intel’s
advanced microprocessors. The voltage identification (VID)
pins program an internal voltage reference (DACOUT) with a
TTL-compatible 5-bit digital-to-analog converter (DAC). The
level of DACOUT also sets the PGOOD and OVP thresholds.
Table 1 specifies the DACOUT voltage for the different
combinations of connections on the VID pins. The VID pins
can be left open for a logic 1 input, since they are internally
pulled to the VAUX pin through 5k ? resistors. Changing the
VID inputs during operation is not recommended and could
toggle the PGOOD signal and exercise the overvoltage
protection. The output voltage program is Intel VRM8.5
compatible.
TABLE 1. OUT1 OUTPUT VOLTAGE PROGRAM
NOTE: 0 = connected to GND, 1 = open or connected to 3.3V
through pull-up resistors
Application Guidelines
Soft-Start Interval
Initially, the soft-start function clamps the error amplifier’s output
of the PWM converters. This generates PHASE pulses of
increasing width that charge the output capacitor(s). The
resulting output voltages start-up as shown in Figure 5.
The soft-start function controls the output voltage rate of rise
to limit the current surge at start-up. The soft-start interval
and the surge current are programmed by the soft-start
capacitor, C SS . Programming a faster soft-start interval
PIN NAME
NOMINAL
DACOUT
increases the peak surge current. Using the recommended
0.1 μ F soft start capacitors ensure all output voltages ramp
VID3
0
0
0
0
0
0
0
0
0
0
0
1
1
VID2
1
1
1
0
0
0
0
0
0
0
0
1
1
VID1
0
0
0
1
1
1
1
0
0
0
0
1
1
VID0
0
0
0
1
1
0
0
1
1
0
0
1
1
VID25
0
0
1
0
1
0
1
0
1
0
1
0
1
VOLTAGE
1.050
1.050
1.075
1.100
1.125
1.150
1.175
1.200
1.225
1.250
1.275
1.300
1.325
up to their set values in a quick and controlled fashion, while
meeting the system timing requirements.
Shutdown
Neither PWM output switches until the soft-start voltage
(V SS ) exceeds the oscillator’s valley voltage. Additionally, the
reference on each linear’s amplifier is clamped to the soft-
start voltage. Holding the SS24 pin low (with an open drain
or open collector signal) turns off regulators 1, 2 and 3.
Regulator 4 (MCH) will simply drop its output to the
intermediate soft-start level. This output is not allowed to
violate the 2V maximum potential gap to the ATX 3.3V
output.
9
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