参数资料
| 型号： | ISL6523CBZ-T |
| 厂商： | Intersil |
| 文件页数： | 8/16页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR VRM8.5 PWM DUAL 28-SOIC |
| 标准包装： | 1,000 |
| 应用： | 控制器，Intel VRM8.5 |
| 输入电压： | 5 V ~ 15 V |
| 输出数： | 4 |
| 输出电压： | 多重 |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 28-SOIC W |
| 包装： | 带卷 (TR) |
ISL6523
overcurrent latch and generates a soft-started ramp-up of
the outputs 1, 2, and 3.
above 4.0V at T4 and the counter increments to 3. This sets
the fault latch to disable the converter.
UV3
SS13UP
1
CHIP
DISABLED
OC
OC1
4V
LATCH
S Q
R
COUNTER
INHIBIT1,2,3
SSDOWN
0
4V
COUNT
=1
COUNT
=2
COUNT
=3
SS13
R
2V
0.8V
SS24
4V
OV
UV4
SS24UP
POR
R
COUNTER
FAULT
LATCH
S Q
R Q
FAULT
0V
0A
OVERLOAD
APPLIED
R
T0 T1
T2
TIME
T3
T4
OC2
S Q
OC
LATCH
FIGURE 7. OVERCURRENT OPERATION
I PEAK = ----------------------------------------------------
FIGURE 6. FAULT LOGIC - SIMPLIFIED SCHEMATIC
OUT1 Overvoltage Protection
The overvoltage circuit provides protection during the initial
application of power. For voltages on the VCC pin below the
power-on reset (and above ~4V), the output level is
monitored for voltages above 1.3V. Should VSEN1 exceed
this level, the lower MOSFET, Q2, is driven on.
Overcurrent Protection
All outputs are protected against excessive overcurrents.
Both PWM controllers use the upper MOSFET’s on-
resistance, r DS(ON) to monitor the current for protection
against shorted outputs. Both linear regulators monitor their
respective VSEN pins for under-voltage to protect against
excessive currents.
Figure 7 illustrates the overcurrent protection with an overload
on OUT2. The overload is applied at T0 and the current
increases through the inductor (L OUT2 ). At time T1, the OC2
comparator trips when the voltage across Q3 (i D ? r DS(ON) )
exceeds the level programmed by R OCSET . This inhibits
outputs 1, 2, and 3, discharges soft-start capacitor C SS24 with
28 μ A current sink, and increments the counter. Soft-start
capacitor C SS13 is quickly discharged. C SS24 recharges at T2
and initiates a soft-start cycle with the error amplifiers
clamped by soft-start. With OUT2 still overloaded, the inductor
current increases to trip the overcurrent comparator. Again,
this inhibits the outputs, but the soft-start voltage continues
increasing to above 4.0V before discharging. The counter
increments to 2. The soft-start cycle repeats at T3 and trips
the overcurrent comparator. The SS pin voltage increases to
The PWM1 controller operates in the same way as PWM2 to
overcurrent faults. Additionally, the two linear controllers
monitor the VSEN pins for under-voltage. Should excessive
currents cause VSEN3 or VSEN4 to fall below the linear
under-voltage threshold, the respective UV signals set the
OC latch or the FAULT latch, providing respective C SS
capacitors are fully charged. Blanking the UV signals during the
C SS charge interval allows the linear outputs to build above
the under-voltage threshold during normal operation. Cycling
the bias input power off then on resets the counter and the
fault latch.
Resistors (R OCSET1 and R OCSET2 ) program the overcurrent
trip levels for each PWM converter. As shown in Figure 8, the
internal 200 μ A current sink (I OCSET ) develops a voltage across
R OCSET (V SET ) that is referenced to V IN . The DRIVE signal
enables the overcurrent comparator (OVERCURRENT1 or
OVERCURRENT2). When the voltage across the upper
MOSFET (V DS(ON) ) exceeds V SET , the overcurrent
comparator trips to set the overcurrent latch. Both V SET and
V DS are referenced to V IN and a small capacitor across
R OCSET helps V OCSET track the variations of V IN due to
MOSFET switching. The overcurrent function will trip at a peak
inductor current (I PEAK) determined by:
I OCSET × R OCSET
r DS ( ON )
The OC trip point varies with MOSFET’s rDS(ON)
temperature variations. To avoid overcurrent tripping in the
normal operating load range, determine the ROCSET
resistor value from the equation above with:
1. The maximum r DS(ON) at the highest junction temperature
2. The minimum I OCSET from the specification table
8
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