参数资料
| 型号： | ISL6523CBZ-T |
| 厂商： | Intersil |
| 文件页数： | 6/16页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR VRM8.5 PWM DUAL 28-SOIC |
| 标准包装： | 1,000 |
| 应用： | 控制器，Intel VRM8.5 |
| 输入电压： | 5 V ~ 15 V |
| 输出数： | 4 |
| 输出电压： | 多重 |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 28-SOIC W |
| 包装： | 带卷 (TR) |
ISL6523
r DS ( ON )
PGOOD (Pin 8)
PGOOD is an open collector output used to indicate the
status of the output voltages. This pin is pulled low when the
synchronous regulator output is not within ± 10% of the
DACOUT reference voltage or when any of the other outputs
is below its under-voltage threshold.
VID3, VID2, VID1, VID0, VID25 (Pins 3-7)
VID3-25 are the TTL-compatible input pins to the 5-bit DAC.
The logic states of these five pins program the internal
voltage reference (DACOUT). The level of DACOUT sets the
microprocessor core converter output voltage (V OUT1 ), as
well as the corresponding PGOOD and OVP thresholds.
Each VID pin is connected to the VAUX pin through a 5k ?
pull-up resistor.
OCSET1, OCSET2 (Pins 23, 10)
Connect a resistor (R OCSET ) from one of these pins to the
drain of the corresponding upper MOSFET. R OCSET , an
internal 200 μ A current source (I OCSET ), and the upper
MOSFET’s on-resistance (r DS(ON) ) set the converter over-
current (OC) trip point according to the following equation:
I OCSET × R OCSET
I PEAK = ----------------------------------------------------
An overcurrent trip cycles the soft-start function.
The voltage at OCSET1 pin is monitored for power-on reset
(POR) purposes.
PHASE1, PHASE2 (Pins 26, 2)
Connect the PHASE pins to the respective PWM converter’s
upper MOSFET sources. These pins represent the gate
drive return current path and are used to monitor the voltage
drop across the upper MOSFETs for overcurrent protection.
UGATE1, UGATE2 (Pins 27, 1)
Connect UGATE pins to the respective PWM converters’
upper MOSFET gate. These pins provide the gate drive for
the upper MOSFETs.
LGATE1 (Pin 25)
Connect LGATE1 to the synchronous PWM converter’s
lower MOSFET gate. This pin provides the gate drive for the
lower MOSFET.
COMP1 and FB1 (Pins 20, 21)
COMP1 and FB1 are the available external pins of the
synchronous PWM regulator error amplifier. The FB1 pin is
the inverting input of the error amplifier. Similarly, the
COMP1 pin is the error amplifier output. These pins are used
to compensate the voltage-mode control feedback loop of
the synchronous PWM converter.
VSEN1 (Pin 22)
This pin is connected to the synchronous PWM converters’
output voltage. The PGOOD and OVP comparator circuits
use this signal to report output voltage status.
VSEN2 (Pin 11)
Connect this pin to the output of the standard buck PWM
regulator. The voltage at this pin is regulated to a 1.5V level.
This pin is also monitored for under-voltage events.
DRIVE3 (Pin 18)
Connect this pin to the gate/base of a N-type external pass
transistor (MOSFET or bipolar). This pin provides the drive
for the 1.5V regulator’s pass transistor.
VSEN3 (Pin 19)
Connect this pin to the output of the 1.5V linear regulator.
This pin is monitored for undervoltage events.
DRIVE4 (Pin 15)
Connect this pin to the base of an external bipolar transistor.
This pin provides the drive for the 1.8V regulator’s pass
transistor.
VSEN4 (Pin 14)
Connect this pin to the output of the linear 1.8V regulator.
This pin is monitored for undervoltage events.
Description
Operation
The ISL6523 monitors and precisely controls 4 output voltage
levels (Refer to Figures 1, 2, 3). It is designed for
microprocessor computer applications with 3.3V, 5V, and 12V
bias input from an ATX power supply. The IC has 2 PWM and
two linear controllers. The first PWM controller (PWM1) is
designed to regulate the microprocessor core voltage (V OUT1 ).
PWM1 controller drives 2 MOSFETs (Q1 and Q2) in a
synchronous-rectified buck converter and regulates the core
voltage to a level programmed by the 5-bit digital-to-analog
converter (DAC). The second PWM controller (PWM2) is
designed to regulate the AGTL+ bus voltage (V OUT2 ). PWM2
controller drives a MOSFET (Q3) in a standard buck converter
and regulates the output voltage to a level of 1.2V. The two
linear controllers supply the 1.5V advanced graphics port
(AGP) bus power (V OUT3 ) and the 1.8V chipset core power
(V OUT4 ).
Initialization
The ISL6523 automatically initializes in ATX-based systems
upon receipt of input power. The Power-On Reset (POR)
function continually monitors the input supply voltages. The
POR monitors the bias voltage (+12V IN ) at the VCC pin, the
5V input voltage (+5V IN ) at the OCSET1 pin, and the 3.3V
input voltage (+3.3V IN ) at the VAUX pin. The normal level on
OCSET1 is equal to +5V IN less a fixed voltage drop (see
6
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