参数资料
| 型号： | ISL6564AIRZ |
| 厂商： | Intersil |
| 文件页数： | 16/28页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM VM 40-QFN |
| 标准包装： | 500 |
| PWM 型： | 电压模式 |
| 输出数： | 1 |
| 频率 - 最大： | 1.5MHz |
| 占空比： | 66.7% |
| 电源电压： | 4.75 V ~ 5.25 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 40-VFQFN 裸露焊盘 |
| 包装： | 管件 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页当前第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页
ISL6564A
TABLE 1. VOLTAGE IDENTIFICATION (VID) CODES (Continued)
down so that a larger positive spike can be sustained without
VID5
400
mV
0
0
0
VID4
200
mV
1
1
1
VID3
100
mV
1
1
1
VID2
50
mv
0
0
0
VID1
25
mV
1
1
0
VID0
12.5
mV
1
0
1
VDAC
0.8625V
0.8500V
0.8375V
crossing the upper specification limit.
As shown in Figure 8, a current proportional to the average
current in all active channels, I AVG , flows from FB through a
load-line regulation resistor, R FB . The resulting voltage drop
across R FB is proportional to the output current, effectively
creating an output voltage droop with a steady-state value
defined as
0
0
1
1
1
0
0
1
0
1
0
1
0.8250V
0.8125V
V DROOP = I AVG R FB
(EQ. 8)
0
0
0
1
1
1
0
0
0
1
1
1
1
0
0
0
1
0
0.8000V
0.7875V
0.7750V
The regulated output voltage is reduced by the droop voltage
V DROOP . The output voltage as a function of load current is
derived by combining Equation 8 with the appropriate
sample current expression defined by the current sense
method employed.
V OUT = V REF – V OFFSET – ? ------------- ------------------ R FB ?
0
0
0
1
1
1
0
0
0
0
0
0
1
1
0
1
0
1
0.7625V
0.7500V
0.7375V
? I OUT R X ?
? 4 R ISEN ?
(EQ. 9)
0
0
0
0
0
1
0
0
0
0
0
1
1
1
1
0
1
1
1
1
0
1
1
0
0
0
1
0
1
0
0.7250V
0.7125V
0.7000V
0.6875V
0.6750V
Where V REF is the reference voltage, V OFS is the
programmed offset voltage, I OUT is the total output current
of the converter, R ISEN is the sense resistor in the ISEN line,
and R FB is the feedback resistor. R X has a value of DCR,
r DS(ON) , or R SENSE depending on the sensing method.
Output-Voltage Offset Programming
The ISL6564A allows the designer to accurately adjust the
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
0.6625V
0.6500V
0.6375V
0.6250V
0.6125V
0.6000V
0.5875V
0.5750V
0.5625V
0.5500V
0.5375V
0.525V
offset voltage. When a resistor, R OFS , is connected between
OFS to VCC, the voltage across it is regulated to 2.0V. This
causes a proportional current (I OFS ) to flow into OFS. If
R OFS is connected to ground, the voltage across it is
regulated to 0.5V, and I OFS flows out of OFS. A resistor
between DAC and REF, R REF , is selected so that the
product (I OFS x R OFS ) is equal to the desired offset voltage.
These functions are shown in Figure 9.
As it may be noticed in Figure 9, the OFSOUT pin must be
connected to the REF pin for this current injection to function
in ISL6564A. The current flow through R REF creates an
offset at the REF pin, which is ultimately duplicated at the
output of the regulator.
Once the desired output offset voltage has been determined,
use the following formulas to set R OFS :
R OFS = --------------------------
R OFS = ------------------------------
In other cases, the designer may determine that a more
cost-effective solution can be achieved by adding droop.
Droop can help to reduce the output-voltage spike that
results from fast load-current demand changes.
The magnitude of the spike is dictated by the ESR and ESL
of the output capacitors selected. By positioning the no-load
voltage level near the upper specification limit, a larger
negative spike can be sustained without crossing the lower
limit. By adding a well controlled output impedance, the
output voltage under load can effectively be level shifted
16
For Positive Offset (connect R OFS to VCC):
2 × R REF
V OFFSET
For Negative Offset (connect R OFS to GND):
0.5 × R REF
V OFFSET
(EQ. 10)
(EQ. 11)
FN6285.1
March 20, 2007
相关PDF资料 |
PDF描述 |
|---|---|
| ISL6564IR-T | IC REG CTRLR BUCK PWM VM 40-QFN |
| ISL6565BCV-T | IC REG CTRLR BUCK PWM VM 28TSSOP |
| ISL6566AIRZ | IC CTRLR PWM 3PHASE BUCK 40-QFN |
| ISL6566CRZ-T | IC CTLR PWM BUCK 3PHASE 40-QFN |
| ISL6567CRZ | IC REG CTRLR BUCK PWM VM 24-QFN |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ISL6564AIRZ-T | 功能描述:IC REG CTRLR BUCK PWM VM 40-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:275kHz 占空比:50% 电源电压:18 V ~ 110 V 降压:无 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 包装:带卷 (TR) |
| ISL6564CR | 功能描述:IC REG CTRLR BUCK PWM VM 40-QFN RoHS:否 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 标准包装:4,000 系列:- PWM 型:电压模式 输出数:1 频率 - 最大:1.5MHz 占空比:66.7% 电源电压:4.75 V ~ 5.25 V 降压:是 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:无 工作温度:-40°C ~ 85°C 封装/外壳:40-VFQFN 裸露焊盘 包装:带卷 (TR) |
| ISL6564CR-T | 功能描述:IC REG CTRLR BUCK PWM VM 40-QFN RoHS:否 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 标准包装:4,000 系列:- PWM 型:电压模式 输出数:1 频率 - 最大:1.5MHz 占空比:66.7% 电源电压:4.75 V ~ 5.25 V 降压:是 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:无 工作温度:-40°C ~ 85°C 封装/外壳:40-VFQFN 裸露焊盘 包装:带卷 (TR) |
| ISL6564CRZ | 功能描述:电流型 PWM 控制器 LEAD-FREE MULTI-PHASE PWM CONTROLLER W/ 0.525-1.3 VID RoHS:否 制造商:Texas Instruments 开关频率:27 KHz 上升时间: 下降时间: 工作电源电压:6 V to 15 V 工作电源电流:1.5 mA 输出端数量:1 最大工作温度:+ 105 C 安装风格:SMD/SMT 封装 / 箱体:TSSOP-14 |
| ISL6564CRZ-T | 功能描述:电流型 PWM 控制器 LEAD-FREE MULTI-PHASE PWM CONTROLLER W/ 0.525-1.3 VID, T&R RoHS:否 制造商:Texas Instruments 开关频率:27 KHz 上升时间: 下降时间: 工作电源电压:6 V to 15 V 工作电源电流:1.5 mA 输出端数量:1 最大工作温度:+ 105 C 安装风格:SMD/SMT 封装 / 箱体:TSSOP-14 |
发布紧急采购，3分钟左右您将得到回复。