参数资料
型号: ISL6564IR-T
厂商: Intersil
文件页数: 16/27页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM VM 40-QFN
标准包装: 4,000
PWM 型: 电压模式
输出数: 1
频率 - 最大: 1.5MHz
占空比: 66.7%
电源电压: 4.75 V ~ 5.25 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 85°C
封装/外壳: 40-VFQFN 裸露焊盘
包装: 带卷 (TR)
ISL6564
TABLE 1. VOLTAGE IDENTIFICATION (VID) CODES (Continued)
As shown in Figure 8, a current proportional to the average
VID5
0
0
0
VID4
1
1
1
VID3
1
1
1
VID2
0
0
0
VID1
1
1
0
VID0
1
0
1
VDAC
0.8625V
0.8500V
0.8375V
current in all active channels, I AVG , flows from FB through a
load-line regulation resistor, R FB . The resulting voltage drop
across R FB is proportional to the output current, effectively
creating an output voltage droop with a steady-state value
defined as
0
1
1
0
0
0
0.8250V
V DROOP = I AVG R FB
(EQ. 8)
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
0
0
1
0
1
0
0.8125V
0.8000V
0.7875V
0.7750V
The regulated output voltage is reduced by the droop voltage
V DROOP . The output voltage as a function of load current is
derived by combining Equation 8 with the appropriate
sample current expression defined by the current sense
method employed.
V OUT = V REF – V OFFSET – ? ------------- ------------------ R FB ?
R ISEN
0
0
0
1
1
1
0
0
0
0
0
0
1
1
0
1
0
1
0.7625V
0.7500V
0.7375V
? 4 ?
? I OUT R X ?
(EQ. 9)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0.7250V
0.7125V
0.7000V
0.6875V
0.6750V
0.6625V
0.6500V
0.6375V
0.6250V
0.6125V
0.6000V
0.5875V
0.5750V
0.5625V
0.5500V
0.5375V
0.525V
Where V REF is the reference voltage, V OFS is the
programmed offset voltage, I OUT is the total output current
of the converter, R ISEN is the sense resistor in the ISEN line,
and R FB is the feedback resistor. R X has a value of DCR,
r DS(ON) , or R SENSE depending on the sensing method.
Output-Voltage Offset Programming
The ISL6564 allows the designer to accurately adjust the
offset voltage. When a resistor, R OFS , is connected between
OFS to VCC, the voltage across it is regulated to 2.0V. This
causes a proportional current (I OFS ) to flow into OFS. If
R OFS is connected to ground, the voltage across it is
regulated to 0.5V, and I OFS flows out of OFS. A resistor
between DAC and REF, R REF , is selected so that the
product (I OFS x R OFS ) is equal to the desired offset voltage.
These functions are shown in Figure 9.
As it may be noticed in Figure 9, the OFSOUT pin must be
connected to the REF pin for this current injection to function
in ISL6564CR. The current flow through R REF creates an
offset at the REF pin, which is ultimately duplicated at the
output of the regulator.
Once the desired output offset voltage has been determined,
use the following formulas to set R OFS :
2 × R REF
V OFFSET
0.5 × R REF
V OFFSET
In other cases, the designer may determine that a more
cost-effective solution can be achieved by adding droop.
Droop can help to reduce the output-voltage spike that
results from fast load-current demand changes.
The magnitude of the spike is dictated by the ESR and ESL
of the output capacitors selected. By positioning the no-load
voltage level near the upper specification limit, a larger
negative spike can be sustained without crossing the lower
limit. By adding a well controlled output impedance, the
output voltage under load can effectively be level shifted
down so that a larger positive spike can be sustained without
crossing the upper specification limit.
16
For Positive Offset (connect R OFS to VCC):
R OFS = --------------------------
For Negative Offset (connect R OFS to GND):
R OFS = ------------------------------
(EQ. 10)
(EQ. 11)
FN9156.2
December 27, 2004
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