参数资料
型号: ISL6564IR-T
厂商: Intersil
文件页数: 17/27页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM VM 40-QFN
标准包装: 4,000
PWM 型: 电压模式
输出数: 1
频率 - 最大: 1.5MHz
占空比: 66.7%
电源电压: 4.75 V ~ 5.25 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 85°C
封装/外壳: 40-VFQFN 裸露焊盘
包装: 带卷 (TR)
ISL6564
FB
Assuming the microprocessor controls the VID change at 1
bit every T VID , the relationship between the time constant of
R REF and C REF network and T VID is given by Equation 12.
DYNAMIC
DAC
C REF R REF = k T VID
(EQ. 12)
VID D/A
E/A
R REF
REF
VCC
OR
GND
Where, T VID = 4 μ s, k is the number of the internal VID
change cycle. If Typically R REF is selected to be 1k ? , the
allowable delay time for VR to respond to new VID code is 5
VID change cycles (totally 20 μ s), the value of C REF should
be 22nF based on Equation 12.
Operation Initialization
Prior to converter initialization, proper conditions must exist
on the enable inputs and VCC. When the conditions are met,
the controller begins soft-start. Once the output voltage is
2.0V
-
+
+
R OFS
within the proper window of operation, PGOOD asserts
logic 1.
VCC
0.5V
-
GND
ISL6564CR
OFS
Enable and Disable
While in shutdown mode, the PWM outputs are held in a
high-impedance state to assure the drivers remain off. The
FIGURE 9. OUTPUT VOLTAGE OFFSET PROGRAMMING
WITH ISL6564CR
following input conditions must be met before the ISL6564 is
released from shutdown mode.
Dynamic VID
Modern microprocessors need to make changes to their
ISL6564 INTERNAL CIRCUIT
EXTERNAL CIRCUIT
core voltage as part of normal operation. They direct the
core-voltage regulator to do this by making changes to the
VCC
+ 12 V
VID inputs during regulator operation. The power
management solution is required to monitor the DAC inputs
and respond to on-the-fly VID changes in a controlled
POR
CIRCUIT
ENABLE
COMPARATOR
EN
10.7k ?
manner. Supervising the safe output voltage transition within
+
the DAC range of the processor without discontinuity or
disruption is a necessary function of the core-voltage
regulator.
The ISL6564 checks the VID inputs at the three edges of
-
1.23V
1.40k ?
16MHz clock. If the VID code is found to have changed, the
controller waits half of a complete cycle before executing a
12.5mV change. If during the half-cycle wait period, the
difference between DAC level and the new VID code
changes sign, no change is made. If the VID code is more
than 1 bit higher or lower than the DAC (not recommended),
the controller will execute step-up and step down VID
change at a speed of 12.5mV every 4 μ s until VID and DAC
are equal.
In order to ensure the smooth transition of output voltage
during VID change, a VID step change smoothing network
composed of R REF and C REF is required for an ISL6564
based voltage regulator. The selection of R REF is based on
the desired offset as detailed above in Output-Voltage Offset
Programming . The selection of C REF is based on the time
duration for 1 bit VID change and the allowable delay time.
17
ENLL
SOFT START
AND
FAULT LOGIC
FIGURE 10. POWER SEQUENCING USING THRESHOLD-
SENSITIVE ENABLE (EN) FUNCTION
1. The bias voltage applied at VCC must reach the internal
power-on reset (POR) rising threshold. Once this
threshold is reached, proper operation of all aspects of
the ISL6564 is guaranteed. Hysteresis between the rising
and falling thresholds assure that once enabled, the
ISL6564 will not inadvertently turn off unless the bias
voltage drops substantially (see Electrical
Specifications ).
FN9156.2
December 27, 2004
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