参数资料
型号: ISL6566ACRZ
厂商: Intersil
文件页数: 16/28页
文件大小: 0K
描述: IC CTRLR PWM 3PHASE BUCK 40-QFN
标准包装: 500
应用: 控制器,Intel VRM9,VRM10,AMD Hammer 应用
输入电压: 3 V ~ 12 V
输出数: 1
输出电压: 0.8 V ~ 1.6 V
工作温度: 0°C ~ 70°C
安装类型: *
封装/外壳: 40-VFQFN 裸露焊盘
供应商设备封装: *
包装: 管件
ISL6566A
the PHASE and UGATE voltages during a PWM falling edge
and the subsequent UGATE turn-off. If either the UGATE falls
to less than 1.75V above the PHASE or the PHASE falls to less
than +0.8V, the LGATE is released to turn on.
Internal Bootstrap Device
All three integrated drivers feature an internal bootstrap
schottky diode. Simply adding an external capacitor across
the BOOT and PHASE pins completes the bootstrap circuit.
The bootstrap function is also designed to prevent the
bootstrap capacitor from overcharging due to the large
negative swing at the PHASE node. This reduces voltage
stress on the boot to phase pins.
The bootstrap capacitor must have a maximum voltage
rating above PVCC + 5V and its capacitance value can be
chosen from the following equation:
Initialization
Prior to initialization, proper conditions must exist on the
ENLL, EN_PH3, VCC, PVCC and the VID pins. When the
conditions are met, the controller begins soft-start. Once the
output voltage is within the proper window of operation, the
controller asserts PGOOD.
Enable and Disable
While in shutdown mode, the PWM outputs are held in a
high-impedance state. This forces the drivers to short gate-
to-source of the upper and lower MOSFET’s to assure the
MOSFETs remain off. The following input conditions must be
met before the ISL6566 is released from this shutdown
mode.
1. The bias voltage applied at VCC must reach the internal
power-on reset (POR) rising threshold. Once this
C BOOT_CAP ≥ --------------------------------------
Q GATE = ------------------------------------ ? N Q1
Q GATE
? V BOOT_CAP
Q G1 ? PVCC
V GS1
(EQ. 12)
threshold is reached, proper operation of all aspects of
the ISL6566A is guaranteed. Hysteresis between the
rising and falling thresholds assure that once enabled,
the ISL6566A will not inadvertently turn off unless the
bias voltage drops substantially (see Electrical
Specifications ).
where Q G1 is the amount of gate charge per upper MOSFET
at V GS1 gate-source voltage and N Q1 is the number of
control MOSFETs. The ? V BOOT_CAP term is defined as the
allowable droop in the rail of the upper gate drive.
1.6
ISL6566A INTERNAL CIRCUIT
POR
EXTERNAL CIRCUIT
VCC
PVCC1
+ 12 V
1.4
1.2
CIRCUIT
ENABLE
COMPARATOR
10.7k ?
ENLL
+
1.
-
1.40k ?
0.8
0.66V
0.6
0.4
0.2
20nC
Q GATE = 100nC
50nC
SOFT-START
AND
FAULT LOGIC
+
-
EN_PH3
0.0
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.22V
FIGURE 11. POWER SEQUENCING USING THRESHOLD-
? V BOOT_CAP (V)
FIGURE 10. BOOTSTRAP CAPACITANCE vs BOOT RIPPLE
VOLTAGE
Gate Drive Voltage Versatility
The ISL6566A provides the user flexibility in choosing the
gate drive voltage for efficiency optimization. The controller
ties the upper and lower drive rails together. Simply applying
a voltage from 5V up to 12V on PVCC sets both gate drive
rail voltages simultaneously.
16
SENSITIVE ENABLE (ENLL) FUNCTION
2. The voltage on ENLL must be above 0.66V. The ENLL
input allows for power sequencing between the controller
bias voltage and another voltage rail. The enable
comparator holds the ISL6566A in shutdown until the
voltage at ENLL rises above 0.66V. The enable
comparator has 60mV of hysteresis to prevent bounce.
3. The voltage on the EN_PH3 pin must be above 1.22V.
The EN_PH3 input allows for power sequencing between
the controller and the external driver.
4. The driver bias voltage applied at the PVCC pins must
reach the internal power-on reset (POR) rising threshold.
FN9200.2
July 27, 2005
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