参数资料
| 型号： | ISL6567CRZ |
| 厂商： | Intersil |
| 文件页数： | 15/25页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM VM 24-QFN |
| 标准包装： | 75 |
| PWM 型： | 电压模式 |
| 输出数： | 1 |
| 频率 - 最大： | 1.5MHz |
| 占空比： | 66% |
| 电源电压： | 4.9 V ~ 5.5 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 24-VFQFN 裸露焊盘 |
| 包装： | 管件 |
| 产品目录页面： | 1243 (CN2011-ZH PDF) |
ISL6567
threshold. For as long as the ISL6567 is biased, OVP has the
V OFS
V TARGET
V OUT
highest priority, bypassing all other control mechanisms and
acting directly onto the lower MOSFETs, as described.
Disabling the IC via the EN pin does not turn off OVP
protection.
START-UP INTO A PRE-CHARGED OUTPUT
The ISL6567 also has the ability to start up into a pre-charged
output, without causing any unnecessary disturbance. The FB
+
V OFS
REFTRK
ISL6567
V REF
EXT CIRCUIT
pin is monitored during soft-start, and should it be higher than
the equivalent internal ramping reference voltage, the output
drives hold both MOSFETs off. Once the internal ramping
To V TARGET
R S
R P
E/A
+
FB
reference exceeds the FB pin potential, the output drives are
enabled, allowing the output to ramp from the pre-charged
level to the final level dictated by the circuit setting.
-
V OFS
+
-
VDIFF
R 1
OUTPUT PRE-CHARGED:
ABOVE INTERNAL REFERENCE
ABOVE EXTERNAL REFERENCE
BELOW REFERENCE
+
-
VSEN
+
-
X1
+
-
RGND
R P
R S
V O U T ( 1 . 0 V / D I V )
SS (1V/DIV)
V REF R P
V OUT
R P + R S
+
------------- = --------------------
FIGURE 14. OFFSET VOLTAGE TRACKING
-
To V OUT
GND>
OUTPUT INITIALLY
DISCHARGED
EN (5V/DIV)
GND>
Offset tracking can be accomplished via a circuit similar to
that used for coincidental tracking (see Figure 14). The desired
offset can be implemented via a voltage source inserted in line
with the resistor divider present at the REFTRK pin. Since most
offset tracking requirements are subject to fairly broad
tolerances, simple voltage drop sources can be used. Figure 14
exemplifies the use of various counts of forward-biased diodes
or that of a Schottky, although other options are available.
Sequential start-up control is easily implemented via the EN
pin, using either a logic control signal or the ISL6567’s own EN
threshold as a power-good detector for the tracked, or
sequence-triggering, voltage. See Figure 15 for details of
control using the EN pin.
OVERVOLTAGE PROTECTION
Although the normal feedback loop operation naturally
counters overvoltage (OV) events the ISL6567 benefits from a
secondary, fixed threshold overvoltage protection. Should the
output voltage exceed 120% of the reference, the lower
MOSFETs are turned on. Once turned on, the lower MOSFETs
are only turned off when the sensed output voltage drops
below the 110% falling threshold of the OC comparator. The
OVP behavior repeats for as long as the ISL6567 is biased,
should the sensed output voltage rise back above the
designated threshold. The occurrence of an OVP event does
not latch the controller; should the phenomenon be transitory,
the controller resumes normal operation following such an
event.
When operating in external-reference mode, the OVP
monitoring is enabled when the MON pin exceeds its rising
15
FIGURE 15. SOFT-START WAVEFORMS INTO A PRE-CHARGED
OUTPUT CAPACITOR BANK
As shown in Figure 15, while operating in internal reference
mode, should the output be pre-charged to a level exceeding
the circuit’s output voltage setting, the output drives are
enabled at the conclusion of the internal reference ramp,
leading to an abrupt correction in the output voltage down to
the set level.
When operating in external reference mode, should the output
voltage be pre-charged above the regulation level driven by the
external reference, the output drives are fully enabled when
the SS pin levels out at the top of its range.
CONTROL OF ISL6567 OPERATION
The internal power-on reset circuit (POR) prevents the ISL6567
from starting before the bias voltage at VCC and PVCC reach
the rising POR thresholds, as defined in the “Electrical
Specifications” table starting on page 5. The POR levels are
sufficiently high to guarantee that all parts of the ISL6567 can
perform their functions properly once bias is applied to the
part. While bias is below the rising POR thresholds, the
controlled MOSFETs are kept in an off state.
FN9243.4
August 9, 2011
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| ISL6567CRZ-T | 功能描述:IC REG CTRLR BUCK PWM VM 24-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:275kHz 占空比:50% 电源电压:18 V ~ 110 V 降压:无 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 包装:带卷 (TR) |
| ISL6567IRZ | 功能描述:IC REG CTRLR BUCK PWM VM 24-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:275kHz 占空比:50% 电源电压:18 V ~ 110 V 降压:无 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 包装:带卷 (TR) |
| ISL6567IRZS2698 | 功能描述:IC REG CTRLR BUCK PWM VM 24-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:275kHz 占空比:50% 电源电压:18 V ~ 110 V 降压:无 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 包装:带卷 (TR) |
| ISL6567IRZ-T | 功能描述:IC REG CTRLR BUCK PWM VM 24-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:275kHz 占空比:50% 电源电压:18 V ~ 110 V 降压:无 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 包装:带卷 (TR) |
| ISL6567IRZ-TS2698 | 功能描述:IC REG CTRLR BUCK PWM VM 24-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:275kHz 占空比:50% 电源电压:18 V ~ 110 V 降压:无 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 包装:带卷 (TR) |
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