参数资料
型号: ISL6567CRZ
厂商: Intersil
文件页数: 17/25页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM VM 24-QFN
标准包装: 75
PWM 型: 电压模式
输出数: 1
频率 - 最大: 1.5MHz
占空比: 66%
电源电压: 4.9 V ~ 5.5 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: 0°C ~ 70°C
封装/外壳: 24-VFQFN 裸露焊盘
包装: 管件
产品目录页面: 1243 (CN2011-ZH PDF)
ISL6567
90
80
70
60
50
40
30
20
10
0
Δ V IN = 1V
Δ V IN = 2V
Δ V IN = 3V
Δ V IN = 4V
Δ V IN = 5V
Δ V IN = 6V
Δ V IN = 7V
Δ V IN = 8V
7
6
5
4
3
2
1
6
7
8 9
V INmin (V)
10
11
0
6
7
8
9
10
11
I BIASMAX = I VREGMAX ? ---------------------------------------
V – V
FIGURE 18. NORMALIZED MAXIMUM BIAS CURRENT
OBTAINABLE IN PASSIVE CONFIGURATION vs INPUT
VOLTAGE RANGE CHARACTERISTIC; V VCC = 5V
The maximum bias current, I BIAS , that can be obtained via the
internal shunt regulator and a simple external resistor is
characterized in Figure 18 and can also be determined using
Equation 11.
V INMIN – V VCC (EQ. 11)
INMAX VCC
V INmin (V)
FIGURE 19. NORMALIZED RESISTOR VALUE IN PASSIVE
CONFIGURATION; V VCC = 5V
Figure 20 details the normalized maximum power dissipation
R BIAS will be subject to in the given application. To use the
graph provided, find the power dissipation level corresponding
to the minimum input voltage and the input voltage range and
multiply it by the maximum desired bias current to obtain the
maximum power R BIAS will dissipate.
To exemplify the use, for an input voltage ranging from 10V to
14V, find the intersection of the Δ V IN = 4V curve with the
V INmin = 10V mark and project the result on the Y axis to find
the maximum bias current obtainable (approximately 56% of
the maximum current obtainable via the integrated shunt
regulator, I VREG_MAX ).
Once the maximum obtainable bias current, I BIAS_MAX , is
determined, and providing it is greater than the bias current,
I BIAS , required by the circuit, R SHUNT can be determined based
on the lowest input voltage, V INMIN :
150
135
120
105
90
75
60
45
Δ V IN = 1V
Δ V IN = 2V
Δ V IN = 3V
Δ V IN = 4V
Δ V IN = 5V
Δ V IN = 6V
Δ V IN = 7V
Δ V IN = 8V
R BIAS = --------------------------------------
V INMIN – V VCC
I BIAS
(EQ. 12)
30
15
Figure 19 helps with a quick resistor selection based on the
previous guidelines presented. Divide the value thus obtained
by the maximum desired bias current, I BIAS , to obtain the
actual resistor value to be used.
0
6 7 8 9 10 11
V INmin (V)
FIGURE 20. NORMALIZED RESISTOR POWER DISSIPATION (AS
SELECTED IN FIGURE 17) vs MINIMUM INPUT
VOLTAGE; V VCC = 5V
Alternately, the maximum power dissipation inside R BIAS can
be calculated using Equation 13.
P MAXRBIAS = ( V INMAX – V VCC ) ? I BIAS
(EQ. 13)
Maximum power dissipation in the bias resistor will take place
at the upper end of the input voltage range. Select a resistor
with a power dissipation rating above the calculated value and
pay attention to design aspects related to the power
dissipation level of this component. Although Figures 18
17
FN9243.4
August 9, 2011
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