参数资料
| 型号： | ISL6568IRZ-TR5184 |
| 厂商： | Intersil |
| 文件页数： | 19/30页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR PWM 2PHASE BUCK 32-QFN |
| 标准包装： | 6,000 |
| 应用： | 控制器，Intel VRM9，VRM10，AMD Hammer 应用 |
| 输入电压： | 3 V ~ 12 V |
| 输出数： | 1 |
| 输出电压： | 0.84 V ~ 1.6 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-VFQFN 裸露焊盘 |
| 供应商设备封装： | 32-QFN（5x5） |
| 包装： | 带卷 (TR) |
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ISL6568
R OCSET
voltage, V OVP . The fixed voltage, V OVP , is 1.67V when running in
AMD Hammer, or VRM10 modes, and 1.97V for VRM9 mode.
IREF
ISUM
+
ISEN
-
ICOMP
-
V DROOP
+
-
V OCSET
+
OCSET
100uA
Upon successful soft-start, the overvoltage trip level is only DAC
plus 150mV. OVP releases 50mV below its trip point if it was
“DAC plus 150mV” that tripped it, and releases 100mV below its
trip point if it was the fixed voltage, V OVP , that tripped it. Actions
are taken by the ISL6568 to protect the microprocessor load
when an overvoltage condition occurs, until the output voltage
falls back within set limits.
VDIFF
+1V
+
-
OC
At the inception of an overvoltage event, all LGATE signals are
commanded high, and the PGOOD signal is driven low. This
causes the controller to turn on the lower MOSFETs and pull
the output voltage below a level that might cause damage to
the load. The LGATE outputs remain high until VDIFF falls to
VID + 150mV
V OVP
SOFT-START, FAULT
AND CONTROL LOGIC
within the overvoltage limits explained above. The ISL6568 will
continue to protect the load in this fashion as long as the
overvoltage condition recurs.
Once an overvoltage condition ends the ISL6568 continues
normal operation and PGOOD returns high.
Pre-POR Overvoltage Protection
VSEN
RGND
+
-
x1
-
+
-
+
OV
UV
PGOOD
Prior to PVCC and VCC exceeding their POR levels, the ISL6568
is designed to protect the load from any overvoltage events
that may occur. This is accomplished by means of an internal
10k Ω resistor tied from PHASE to LGATE, which turns on the
lower MOSFET to control the output voltage until the
overvoltage event ceases or the input power supply cuts off.
For complete protection, the low side MOSFET should have a
gate threshold well below the maximum voltage rating of the
load/microprocessor.
0.82 x DAC
ISL6568 INTERNAL CIRCUITRY
In the event that during normal operation the PVCC or VCC
voltage falls back below the POR threshold, the pre-POR
FIGURE 13. POWER GOOD AND PROTECTION CIRCUITRY
Power-Good Signal
The power good pin (PGOOD) is an open-drain logic output that
transitions high when the converter is operating after soft-
start. PGOOD pulls low during shutdown and releases high
after a successful soft-start. PGOOD transitions low when an
undervoltage, overvoltage, or overcurrent condition is detected
or when the controller is disabled by a reset from ENLL, POR,
or one of the no-CPU VID codes. If after an undervoltage or
overvoltage event occurs the output returns to within under
and overvoltage limits, PGOOD will return high.
Undervoltage Detection
The undervoltage threshold is set at 82% of the VID code.
When the output voltage (VSEN-RGND) is below the
undervoltage threshold, PGOOD gets pulled low. No other
action is taken by the controller. PGOOD will return high if the
output voltage rises above 85% of the VID code.
Overvoltage Protection
The ISL6568 constantly monitors the difference between the
VSEN and RGND voltages to detect if an overvoltage event
occurs. During soft-start, while the DAC is ramping up, the
overvoltage trip level is the higher of DAC plus 150mV or a fixed
19
overvoltage protection circuitry reactivates to protect from any
more pre-POR overvoltage events.
Open Sense Line Protection
In the case that either of the remote sense lines, VSEN or GND,
become open, the ISL6568 is designed to detect this and shut
down the controller. This event is detected by monitoring the
voltage on the IREF pin, which is a local version of V OUT sensed
at the outputs of the inductors.
If VSEN or RGND become opened, VDIFF falls, causing the duty
cycle to increase and the output voltage on IREF to increase. If
the voltage on IREF exceeds “VDIFF+1V”, the controller will
shut down. Once the voltage on IREF falls below “VDIFF+1V”,
the ISL6568 will restart at the beginning of soft-start.
Overcurrent Protection
The ISL6568 detects overcurrent events by comparing the
droop voltage, V DROOP , to the OCSET voltage, V OCSET , as
shown in Figure 13. The droop voltage, set by the external
current sensing circuitry, is proportional to the output current
as shown in Equation 7. A constant 100μA flows through
R OCSET , creating the OCSET voltage. When the droop voltage
exceeds the OCSET voltage, the overcurrent protection circuitry
activates. Since the droop voltage is proportional to the output
current, the overcurrent trip level, I MAX , can be set by selecting
the proper value for R OCSET , as shown in Equation 14.
FN9187.5
January 12, 2012
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| ISL6569ACB | 功能描述:IC REG CTRLR BUCK PWM 24-SOIC RoHS:否 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:500kHz 占空比:100% 电源电压:8.2 V ~ 30 V 降压:无 升压:无 回扫:是 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:0°C ~ 70°C 封装/外壳:8-DIP（0.300"，7.62mm） 包装:管件 产品目录页面:1316 (CN2011-ZH PDF) |
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| ISL6569ACBZ-T | 功能描述:IC REG CTRLR BUCK PWM 24-SOIC RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:275kHz 占空比:50% 电源电压:18 V ~ 110 V 降压:无 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 包装:带卷 (TR) |
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