参数资料
| 型号： | ISL6568IRZ-TR5184 |
| 厂商： | Intersil |
| 文件页数： | 24/30页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR PWM 2PHASE BUCK 32-QFN |
| 标准包装： | 6,000 |
| 应用： | 控制器，Intel VRM9，VRM10，AMD Hammer 应用 |
| 输入电压： | 3 V ~ 12 V |
| 输出数： | 1 |
| 输出电压： | 0.84 V ~ 1.6 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-VFQFN 裸露焊盘 |
| 供应商设备封装： | 32-QFN（5x5） |
| 包装： | 带卷 (TR) |
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ISL6568
C 2 (OPTIONAL)
In Equation 29, L is the per-channel filter inductance divided by
the number of active channels; C is the sum total of all output
capacitors; ESR is the equivalent series resistance of the bulk
R C
C C
COMP
output filter capacitance; and V P-P is the peak-to-peak
sawtooth signal amplitude as described in the “Electrical
FB
ISL6568
Once selected, the compensation values in Equations 29
assure a stable converter with reasonable transient
performance. In most cases, transient performance can be
R FB
VDIFF
improved by making adjustments to R C . Slowly increase the
value of R C while observing the transient performance on an
oscilloscope until no further improvement is noted. Normally,
FIGURE 20. COMPENSATION CONFIGURATION FOR
LOAD-LINE REGULATED ISL6568 CIRCUIT
Since the system poles and zero are affected by the values of
the components that are meant to compensate them, the
solution to the system equation becomes fairly complicated.
Fortunately, there is a simple approximation that comes very
close to an optimal solution. Treating the system as though it
were a voltage-mode regulator, by compensating the L-C poles
and the ESR zero of the voltage mode approximation, yields a
solution that is always stable with very close to ideal transient
performance.
Select a target bandwidth for the compensated system, f 0 . The
target bandwidth must be large enough to assure adequate
transient performance, but smaller than 1/3 of the per-
channel switching frequency. The values of the compensation
components depend on the relationships of f 0 to the L-C pole
frequency and the ESR zero frequency. For each of the
following three, there is a separate set of equations for the
compensation components.
C C will not need adjustment. Keep the value of C C from
Equations 29 unless some performance issue is noted.
The optional capacitor C 2 , is sometimes needed to bypass
noise away from the PWM comparator (See Figure 20). Keep a
position available for C 2 , and be prepared to install a
high-frequency capacitor of between 22pF and 150pF in case
any leading edge jitter problem is noted.
Output Filter Design
The output inductors and the output capacitor bank together to
form a low-pass filter responsible for smoothing the pulsating
voltage at the phase nodes. The output filter also must provide
the transient energy until the regulator can respond. Because
it has a low bandwidth compared to the switching frequency,
the output filter limits the system transient response. The
output capacitors must supply or sink load current while the
current in the output inductors increases or decreases to meet
the demand.
In high-speed converters, the output capacitor bank is usually
the most costly (and often the largest) part of the circuit. Output
filter design begins with minimizing the cost of this part of the
------------------- > f 0
R C = R FB ------------------------------------
0.66V
2 π V PP R FB f 0
------------------- ≤ f 0 < ------------------------------
Case 1:
Case 2:
1
2 π LC
2 π f 0 V pp LC
IN
0.66V IN
C C = ------------------------------------
1 1
2 π LC 2 π C ( ESR )
circuit. The critical load parameters in choosing the output
capacitors are the maximum size of the load step, Δ I, the
load-current slew rate, di/dt, and the maximum allowable
output-voltage deviation under transient loading, Δ V MAX .
Capacitors are characterized according to their capacitance,
ESR, and ESL (equivalent series inductance).
At the beginning of the load transient, the output capacitors
supply all of the transient current. The output voltage will
initially deviate by an amount approximated by the voltage
drop across the ESL. As the load current increases, the voltage
R C = R FB --------------------------------------------
0.66 V
( 2 π ) 2 f 02 V PP R FB LC
V PP ( 2 π ) 2 f 02 LC
IN
0.66V IN
C C = -------------------------------------------------------------
(EQ. 29)
drop across the ESR increases linearly until the load current
reaches its final value. The capacitors selected must have
sufficiently low ESL and ESR so that the total output-voltage
deviation is less than the allowable maximum. Neglecting the
contribution of inductor current and regulator response, the
output voltage initially deviates by an amount as shown by
f 0 > ------------------------------
0.66 V IN ( ESR )
Δ V ≈ ( ESL ) ----- + ( ESR ) Δ I
2 π V PP R FB f 0 L
Case 3:
1
2 π C ( ESR )
2 π f 0 V pp L
R C = R FB ------------------------------------------
0.66V IN ( ESR ) C
C C = -------------------------------------------------
24
Equation 30.
di (EQ. 30)
dt
The filter capacitor must have sufficiently low ESL and ESR so
that Δ V < Δ V MAX .
Most capacitor solutions rely on a mixture of high frequency
capacitors with relatively low capacitance in combination with
FN9187.5
January 12, 2012
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| ISL6569ACB | 功能描述:IC REG CTRLR BUCK PWM 24-SOIC RoHS:否 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:500kHz 占空比:100% 电源电压:8.2 V ~ 30 V 降压:无 升压:无 回扫:是 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:0°C ~ 70°C 封装/外壳:8-DIP（0.300"，7.62mm） 包装:管件 产品目录页面:1316 (CN2011-ZH PDF) |
| ISL6569ACB-T | 功能描述:IC REG CTRLR BUCK PWM 24-SOIC RoHS:否 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:500kHz 占空比:100% 电源电压:8.2 V ~ 30 V 降压:无 升压:无 回扫:是 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:0°C ~ 70°C 封装/外壳:8-DIP（0.300"，7.62mm） 包装:管件 产品目录页面:1316 (CN2011-ZH PDF) |
| ISL6569ACBZ | 功能描述:IC REG CTRLR BUCK PWM 24-SOIC RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:275kHz 占空比:50% 电源电压:18 V ~ 110 V 降压:无 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 包装:带卷 (TR) |
| ISL6569ACBZ-T | 功能描述:IC REG CTRLR BUCK PWM 24-SOIC RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:275kHz 占空比:50% 电源电压:18 V ~ 110 V 降压:无 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 包装:带卷 (TR) |
| ISL6569ACR | 功能描述:IC REG CTRLR BUCK PWM 32-QFN RoHS:否 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:500kHz 占空比:100% 电源电压:8.2 V ~ 30 V 降压:无 升压:无 回扫:是 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:0°C ~ 70°C 封装/外壳:8-DIP（0.300"，7.62mm） 包装:管件 产品目录页面:1316 (CN2011-ZH PDF) |
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