参数资料
型号: ISL6615AIBZ
厂商: Intersil
文件页数: 3/12页
文件大小: 0K
描述: IC MOSFET DRVR SYNC HF 6A 8-SOIC
标准包装: 980
配置: 高端和低端,同步
输入类型: PWM
延迟时间: 10ns
电流 - 峰: 2.5A
配置数: 1
输出数: 2
高端电压 - 最大(自引导启动): 36V
电源电压: 6.8 V ~ 13.2 V
工作温度: -40°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
供应商设备封装: 8-SOIC
包装: 管件
ISL6615A
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
ISL6615ACBZ
ISL6615ACRZ
ISL6615AIBZ
ISL6615AIRZ
ISL6615AFRZ
PART
MARKING
6615A CBZ
615A
6615A IBZ
15AI
15AF
TEMP.
RANGE (°C)
0 to +70
0 to +70
-40 to +85
-40 to +85
-40 to +125
PACKAGE
(Pb-free)
8 Ld SOIC
10 Ld 3x3 DFN
8 Ld SOIC
10 Ld 3x3 DFN
10 Ld 3x3 DFN
PKG.
DWG. #
M8.15
L10.3x3
M8.15
L10.3x3
L10.3x3
NOTES:
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-
free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL6615A . For more information on MSL please see techbrief TB363 .
Pin Configurations
ISL6615A
(8 LD SOIC)
TOP VIEW
ISL6615A
(10 LD 3x3 DFN)
TOP VIEW
UGATE
BOOT
1
2
8
7
PHASE
PVCC
UGATE
BOOT
1
2
10 PHASE
9 PVCC
PWM
GND
3
4
6
5
VCC
LGATE
N/C
PWM
3
4
GND
8 N/C
7 VCC
GND
5
6 LGATE
*RECOMMEND TO CONNECT PIN 3 TO GND AND PIN 8 TO PVCC
Functional Pin Descriptions
PACKAGE PIN #
PIN
SOIC
1
2
DFN
1
2
SYMBOL
UGATE
BOOT
FUNCTION
Upper gate drive output. Connect to gate of high-side power N-Channel MOSFET.
Floating bootstrap supply pin for the upper gate drive. Connect the bootstrap capacitor between this pin and the
PHASE pin. The bootstrap capacitor provides the charge to turn on the upper MOSFET. See the Internal Bootstrap
Device “TIMING DIAGRAM” on page 6 under Description for guidance in choosing the capacitor value.
-
3
3, 8
4
N/C
PWM
No Connection. Recommend to connect pin 3 to GND and pin 8 to PVCC.
The PWM signal is the control input for the driver. The PWM signal can enter three distinct states during operation, see the
“TIMING DIAGRAM” on page 6 section under Description for further details. Connect this pin to the PWM output of the
controller.
4
5
6
7
5
6
7
9
GND
LGATE
VCC
PVCC
Bias and reference ground. All signals are referenced to this node. It is also the power ground return of the driver.
Lower gate drive output. Connect to gate of the low-side power N-Channel MOSFET.
Its operating range is +6.8V to 13.2V. Place a high quality low ESR ceramic capacitor from this pin to GND.
This pin supplies power to both upper and lower gate drives. Its operating range is +4.5V to 13.2V. Place a high quality
low ESR ceramic capacitor from this pin to GND.
8
10
PHASE
Connect this pin to the SOURCE of the upper MOSFET and the DRAIN of the lower MOSFET. This pin provides a return
path for the upper gate drive.
9
11
PAD
Connect this pad to the power ground plane (GND) via thermally enhanced connection.
3
FN6608.2
April 13, 2012
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