参数资料
| 型号： | ISL78225ANEZ-T |
| 厂商： | Intersil |
| 文件页数： | 16/22页 |
| 文件大小： | 0K |
| 描述： | IC PWM CONTROLLER |
| 标准包装： | 1,000 |
| 系列： | * |
ISL78225
Oscillator and Synchronization
The switching frequency is determined by the selection of the
frequency-setting resistor, R FS , connected from the FS pin to
GND. Equation 4 is provided to assist in selecting the correct
resistor value.
Current Sensing
The ISL78225 senses the current continuously for fast response.
It supports both sense resistor and inductor DCR current sensing
methods. The sensed current for each active channel will be used
for loop control, phase current balance, individual channel
10 ? 1
---------- – 5X10 ?
? f ?
R FS = 4X10
SW
– 8
(EQ. 4)
overcurrent protection and total average current protection. The
internal circuitry, (shown in Figures 20 and 21), represents a single
channel. This circuitry is repeated for each channel, but may not
Where f SW is the switching frequency of each phase. Figure 19
shows the relationship between R FS and switching frequency.
1000
900
800
700
600
500
400
300
200
100
be active depending on the status of the PWM3 and PWM4 pin
voltage.
Peak current mode control is implemented by feeding back the
current output of the current sense amplifier (CSA) to the
regulator control loop. Individual channel peak current limit is
implemented by comparing the CSA output current with 160μA.
When the peak current limit comparator is tripped, the PWM
ON-pulse is terminated and the IC is latched off.
Sense Resistor Current Sensing
A sense resistor can be placed in series with the power inductor.
As shown in Figure 20, The ISL78225 acquires the channel
current information by sensing the voltage signal across the
sense resistor. Because the voltage on both the positive input
and the negative input of the current sense amplifier (CSA) are
0
0
100 200 300 400 500
R FS (k Ω )
FIGURE 19. R FS vs SWITCHING FREQUENCY
600
forced to be equal, the voltage across R SET is equivalent to the
voltage drop across the R SEN resistor. The resulting current into
the ISENxP pin is proportional to the channel current, I L .
Equation 5 for I SEN is derived where I L is the channel current:
I SEN = I L ? ----------------
The maximum frequency at each PWM output is 1MHz. If the FS
pin is accidentally shorted to GND or connected to a low
impedance node, the internal circuits will detect this fault
condition and fold back the switching frequency to the 75kHz
minimal value.
The ISL78225 contains a phase lock loop (PLL) circuit and has
frequency synchronization capability by simply connecting the
R SEN
R I SE T
VIN
R SEN
L
(EQ. 5)
VOUT
SYNC pin to an external square pulse waveform (typically 20% to
80% duty cycle). In normal operation, the external SYNC
frequency needs to be at least 20% faster than the internal
oscillator frequency setting. The ISL78225 will synchronize its
switching frequency to the fundamental frequency of the input
waveform. The frequency synchronization feature will
synchronize the rising edge of the PWM1 clock signal with the
I SEN
R SET
SENSE RESISTOR
CURRENT SENSING
rising edge of the external clock signal at the SYNC pin.
I SEN
CSA
ISEN(n)P
The PLL is compensated with a series resistor-capacitor (Rc and
Cc) from the PLL_COMP pin to GND and a capacitor (Cp) from
PLL_COMP to GND. Typical values are Rc = 6.8k ? , Cc = 6.8nF,
Cp = 1nF. The typical lock time is around 0.5ms.
The CLK_OUT pin provides a square pulse waveform at the
switching frequency. The amplitude is 5V with approximately
40% positive duty cycle, and the rising edge is synchronized with
the leading edge of PWM1.
16
ISEN(n)N
ISL78225 INTERNAL CIRCUITS
FIGURE 20. SENSE RESISTOR CURRENT SENSING
FN7909.3
February 11, 2014
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