参数资料
| 型号： | ISL78225ANEZ-T |
| 厂商： | Intersil |
| 文件页数： | 2/22页 |
| 文件大小： | 0K |
| 描述： | IC PWM CONTROLLER |
| 标准包装： | 1,000 |
| 系列： | * |
ISL78225
Pin Configuration
ISL78225
(44 LD 10x10 EP-TQFP)
TOP VIEW
FS
1
44 43 42 41 40 39 38 37 36 35 34
33
VIN
SS
COMP
FB
VREF2
GND
SLOPE
PLL_COMP
SYNC
CLK_OUT
2
3
4
5
6
7
8
9
10
32
31
30
29
28
27
26
25
24
DNC
DNC
ISEN4P
ISEN4N
ISEN2P
ISEN2N
DNC
DNC
ISEN3P
PWM_INV
11 23
12 13 14 15 16 17 18 19 20 21 22
ISEN3N
Functional Pin Descriptions
PIN #
1
2
3
4
5
6
7
8
9
10
11
SYMBOL
FS
SS
COMP
FB
VREF2
GND
SLOPE
PLL_COMP
SYNC
CLK_OUT
PWM_INV
2
DESCRIPTION
A resistor placed from FS to ground will set the PWM switching frequency.
Use this pin to set-up the desired soft-start time. A capacitor placed from SS to ground will set up the soft-start
ramp rate and in turn determine the soft-start time.
The output of the transconductance amplifier. Place the compensation network between COMP and GND for
compensation loop design.
The inverting input of the transconductance amplifier. A resistor network should be placed between the FB pin and
output rail to set the output voltage.
External reference input to the transconductance amplifier. When the VREF2 pin voltage drops below 1.8V, the
internal reference will be shifted from 2V to VREF2. The VREF2 voltage can be programmed by connecting a
resistor divider network from VCC or VIN.
Bias and reference ground for the IC.
This pin programs the slope of the internal slope compensation. A resistor should be connected from the SLOPE
pin to GND. Please refer to “Adjustable Slope Compensation” on page 19 for how to choose the resistor value.
This pin serves as the compensation node for the PLL. A second order passive loop filter connected between
PLL_COMP pin and GND compensates the PLL feedback loop.
Frequency synchronization pin. Connecting the SYNC pin to an external square pulse waveform (typically 20% to
80% duty cycle) will synchronize the converter switching frequency to the fundamental frequency of the input
waveform. If SYNC function is not used, tie the SYNC pin to GND. A 500nA current source is connected internally
to pull-down the SYNC pin if it is left open.
This pin provides a clock signal to synchronize with another ISL78225. This provides scalability and flexibility. The
rising edge signal on the CLKOUT pin is in phase with the leading edge of the PWM1 signal.
This pin determines the polarity of the PWM output signal. Pulling this pin to GND will force normal operation with
inverting MOSFET drivers. Pulling this pin to VCC will invert the PWM signal for operation with non-inverting
MOSFET drivers. This function provides the flexibility for the ISL78225 to work with different drivers.
FN7909.3
February 11, 2014
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ISL78225EVAL1Z | 制造商:Intersil Corporation 功能描述:ISL78225 EVALUATION BOARD 1 - 44 LEAD - TQFP - ROHS COMPLIAN - Bulk |
| ISL78228 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Dual 800mA Low Quiescent Current 2.25MHz High Efficiency Synchronous Buck Regulator |
| ISL78228ARZ | 功能描述:IC REG BUCK SYNC ADJ DL 10-DFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 开关稳压器 系列:- 标准包装:1 系列:- 类型:升压（升压） 输出类型:固定 输出数:1 输出电压:4.5V 输入电压:2.65 V ~ 4.35 V PWM 型:电流模式 频率 - 开关:3.5MHz 电流 - 输出:800mA 同步整流器:是 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:9-UFBGA，DSBGA 包装:Digi-Reel® 供应商设备封装:9-DSBGA（1.2x1.3） 其它名称:296-29764-6 |
| ISL78228ARZ-T | 功能描述:IC REG BUCK SYNC ADJ DL 10-DFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 开关稳压器 系列:- 标准包装:1 系列:- 类型:升压（升压） 输出类型:固定 输出数:1 输出电压:4.5V 输入电压:2.65 V ~ 4.35 V PWM 型:电流模式 频率 - 开关:3.5MHz 电流 - 输出:800mA 同步整流器:是 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:9-UFBGA，DSBGA 包装:Digi-Reel® 供应商设备封装:9-DSBGA（1.2x1.3） 其它名称:296-29764-6 |
| ISL78233ARZ | 制造商:Intersil Corporation 功能描述:IC REG BUCK SYNC ADJ 3A 16QFN |
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