参数资料
| 型号： | ISL78225ANEZ-T |
| 厂商： | Intersil |
| 文件页数： | 18/22页 |
| 文件大小： | 0K |
| 描述： | IC PWM CONTROLLER |
| 标准包装： | 1,000 |
| 系列： | * |
ISL78225
will bring down the pre-set channel current limit to 2/3 of its
original value (160μA). If any of the phase’s sensed current hit
the 2/3 of pre-set channel current limit threshold (i.e., 106.7μA),
all the phases will be added back instantly. After a fixed 1.5ms
delay, the phase dropping circuit will be activated and the system
will react to drop the phase number to the correct value.
During phase adding, when either phase hits the pre-set channel
current limit, there will be 200μs blanking time such that
per-channel OCP will not be triggered during this blanking time.
Diode Emulation at Very Light Load Condition
When phase dropping is asserted and the minimum phase
operation is 2 phases, if the load is still reducing and
synchronous boost structure is used, the ISL78225 controller will
enter into forced cycle-by-cycle diode emulation mode. The PWM
output will be tri-stated when the inductor current falls to zero,
such that the synchronous MOSFET can be turned off accordingly
cycle-by-cycle for forced diode emulation. This cycle-by-cycle
diode emulation scheme will only be asserted when two
conditions are met:
1. The PWM_TRI pin voltage is logic HIGH.
2. Only two phases are running either by phase dropping or
initial configuration.
By utilizing the cycle-by-cycle diode emulation scheme in this
way, negative current is prevented and the system can still
optimize the efficiency even at very light load conditions.
Pulse Skipping at Deep Light Load Condition
If the converter enters diode emulation mode and the load is still
reducing, eventually pulse skipping will occur to increase the
deep light load efficiency.
Adjustable Slope Compensation
For a boost converter working in current mode control, slope
compensation is needed when steady state duty cycle is larger
than 50%. When slope compensation is too low, the converter
can suffer from jitter or oscillation. On the other hand, over
compensation of the slope will cause the reduction of the phase
margin. Therefore, proper design of the slope compensation is
needed.
The ISL78225 features adjustable slope compensation by
setting the resistor value R SLOPE from the SLOPE pin to GND.
This function will ease the compensation design and provide
more flexibility in choosing the external components.
For current mode control, typically we need the compensation
slope m A to be 50% of the inductor current down ramp slope m B
when the lower MOSFET is off. Equation 9 shows how to choose
the suitable resistor value.
Fault Monitoring and Protection
The ISL78225 actively monitors input/output voltage and current to
detect fault conditions. Fault monitors trigger protective measures
to prevent damage to the load. Common power-good indicator pin
(PGOOD pin) and VIN_OVB, VOUT_OVB pins are provided for linking
to external system monitors.
PGOOD Signal
The PGOOD pin is an open-drain logic output to indicate that the
soft-start period is completed and the output voltage is within the
specified range. This pin is pulled low during soft-start and
releases high after a successful soft-start. PGOOD will be pulled
low when a UV/OV/OC/OT fault occurs.
Input Overvoltage Detection
The ISL78225 utilizes VIN_SEN and VIN_OVB pins to deal with a
high input voltage. The VIN_SEN pin is used for sensing the input
voltage. A resistor divider network is connected between this pin
and the boost power stage input voltage rail. When the voltage
on VIN_SEN is higher than 2.4V, the open drain output VIN_OVB
pin will be pulled low to indicate an input overvoltage condition,
The V IN overvoltage sensing threshold can be programmed by
changing the resistor values, and hysteresis voltage of the
internal comparator is fixed to be 100mV.
Output Undervoltage Detection
The undervoltage threshold is set at 80% of the internal voltage
reference. When the output voltage at the FB pin is below the
undervoltage threshold minus the hysteresis, PGOOD is pulled
low. When the output voltage comes back to 80% of the
reference voltage, PGOOD will return back to high.
Output Overvoltage Detection/Protection
The ISL78225 overvoltage detection circuit is active after time t 2
in Figure 14 on page 13. The OV trip point is set to 120% of the
internal reference level. Once an overvoltage condition is
detected, the PGOOD will be pulled low but the controller will
continue to operate.
The ISL78225 also provides the flexibility for output overvoltage
protection by utilizing the VOUT_SEN and VOUT_OVB pins. The
VOUT_SEN pin is used for sensing the output voltage. A resistor
divider network is connected between this pin and the boost
power stage output voltage rail. When the voltage on VOUT_SEN
is higher than 2.4V, the open drain output VOUT_OVB will be
pulled low, and the ISL78225 IC will be latched off to indicate an
output overvoltage condition. The V OUT overvoltage sensing
threshold can be programmed by changing the resistor values.
Overcurrent Protection
ISL78225 has two levels of overcurrent protection. Each phase is
protected from an overcurrent condition by limiting its peak
1.136x10 xLxR SET
( V OUT – V IN ) ( R SEN )
6
R SLOPE = ---------------------------------------------------- ( Ω )
18
(EQ. 9)
current, and the combined total current is protected on an
average basis.
For the individual channel overcurrent protection, the ISL78225
continuously compares the CSA output current of each channel
with a 160μA reference current. If any channel’s current trips the
current limit comparator, the ISL78225 will be shut down.
FN7909.3
February 11, 2014
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