参数资料
型号: ISL8103CRZ
厂商: Intersil
文件页数: 16/28页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM VM 40-QFN
标准包装: 50
PWM 型: 电压模式
输出数: 1
频率 - 最大: 1.5MHz
占空比: 66.6%
电源电压: 4.75 V ~ 12.6 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: 0°C ~ 70°C
封装/外壳: 40-VFQFN 裸露焊盘
包装: 管件
ISL8103
Fault Monitoring and Protection
t SS = --------------------------------------------
64 + DAC ? 1280
F SW
(EQ. 12)
The ISL8103 actively monitors output voltage and current to
detect fault conditions. Fault monitors trigger protective
For example, a regulator with 450kHz switching frequency
having REF voltage set to 1.2V has t SS equal to 3.55ms.
measures to prevent damage to the load.
A 100mV offset exists on the remote-sense amplifier at the
beginning of soft-start and ramps to zero during the first 640
* Connect DROOP to IREF
to disable the Droop feature.
R OCSET
cycles of soft-start (704 cycles following enable). This
DROOP*
ICOMP
-
V OCSET
+
OCSET
prevents the large inrush current that would otherwise occur
should the output voltage start out with a slight negative
IREF
+
bias.
The ISL8103 also has the ability to start up into a
ISUM
ISEN
-
-
V DROOP
+
100μA
pre-charged output as shown in Figure 12, without causing
any unnecessary disturbance. The FB pin is monitored
during soft-start, and should it be higher than the equivalent
internal ramping reference voltage, the output drives hold
VDIFF
+1V
+
-
OC
both MOSFETs off. Once the internal ramping reference
exceeds the FB pin potential, the output drives are enabled,
allowing the output to ramp from the pre-charged level to the
final level dictated by the reference setting. Should the
output be pre-charged to a level exceeding the reference
setting, the output drives are enabled at the end of the
soft-start period, leading to an abrupt correction in the output
DAC + 150mV
V OVP
SOFT-START, FAULT
AND CONTROL LOGIC
voltage down to the “reference set” level.
-
OUTPUT PRECHARGED
ABOVE DAC LEVEL
OUTPUT PRECHARGED
BELOW DAC LEVEL
VSEN
RGND
+
-
x1
+
-
+
OV
UV
PGOOD
0.82 x DAC
ISL8103 INTERNAL CIRCUITRY
GND>
V OUT (0.5V/DIV)
FIGURE 13. POWER-GOOD AND PROTECTION CIRCUITRY
GND>
T1 T2
T3
ENLL (5V/DIV)
One common power good indicator is provided for linking to
external system monitors. The schematic in Figure 13
outlines the interaction between the fault monitors and the
FIGURE 12. SOFT-START WAVEFORMS FOR ISL8103-BASED
MULITPHASE CONVERTER
16
power-good signal
Power-Good Signal
The power good pin (PGOOD) is an open-drain logic output
that transitions high when the converter is operating after
soft-start. PGOOD pulls low during shutdown and releases
high after a successful soft-start. PGOOD transitions low
when an undervoltage, overvoltage, or overcurrent condition
is detected or when the controller is disabled by a reset from
ENLL or POR. If after an undervoltage or overvoltage event
occurs the output returns to within under and overvoltage
limits, PGOOD will return high.
FN9246.1
July 21, 2008
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ISL8104 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Synchronous Buck Pulse-Width Modulator (PWM) Controller