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| 型号： | ISL8103CRZ |
| 厂商： | Intersil |
| 文件页数： | 22/28页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM VM 40-QFN |
| 标准包装： | 50 |
| PWM 型： | 电压模式 |
| 输出数： | 1 |
| 频率 - 最大： | 1.5MHz |
| 占空比： | 66.6% |
| 电源电压： | 4.75 V ~ 12.6 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 40-VFQFN 裸露焊盘 |
| 包装： | 管件 |
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ISL8103
Compensating the Converter operating without
Load-Line Regulation
The ISL8103 multiphase converter operating without load
C 2
line regulation behaves in a similar manner to a
voltage-mode controller. This section highlights the design
COMP
R 2
C 1
R 3
C 3
consideration for a voltage-mode controller requiring external
-
compensation. To address a broad range of applications, a
type-3 feedback network is recommended (see Figure 20).
E/A
+
FB
R 1
C 2
VREF
R 2
C 1
COMP
VDIFF
C 3
FB
-
+
RGND
R 3
R 1
VDIFF
ISL8103
VSEN
OSCILLATOR
V IN
V OUT
FIGURE 20. COMPENSATION CONFIGURATION FOR
NON-LOAD-LINE REGULATED ISL8103 CIRCUIT
PWM
CIRCUIT
V OSC
Figure 21 highlights the voltage-mode control loop for a
HALF-BRIDGE
UGATE
L
DCR
synchronous-rectified buck converter, applicable, with a
small number of adjustments, to the mulitphase ISL8103
circuit. The output voltage (V OUT ) is regulated to the reference
voltage, VREF, level. The error amplifier output (COMP pin
DRIVE
PHASE
LGATE
C
ESR
voltage) is compared with the oscillator (OSC) modified
saw-tooth wave to provide a pulse-width modulated wave with
an amplitude of V IN at the PHASE node. The PWM wave is
ISL8103
EXTERNAL CIRCUIT
d MAX ? V IN ? F LC
smoothed by the output filter (L and C). The output filter
capacitor bank’s equivalent series resistance is represented by
the series resistor E.
The modulator transfer function is the small-signal transfer
function of V OUT /V COMP . This function is dominated by a DC
gain, given by d MAX V IN /V OSC , and shaped by the output
filter, with a double pole break frequency at F LC and a zero at
F CE . For the purpose of this analysis, L and DCR represent
the individual channel inductance and its DCR divided by 3
(equivalent parallel value of the three output inductors), while
C and ESR represents the total output capacitance and its
equivalent series resistance.
FIGURE 21. VOLTAGE-MODE BUCK CONVERTER
COMPENSATION DESIGN
C 3 ) in Figure 20 and 21. Use the following guidelines for
locating the poles and zeros of the compensation network:
1. Select a value for R 1 (1k Ω to 5k Ω , typically). Calculate
value for R 2 for desired converter bandwidth (F 0 ).
V OSC ? R 1 ? F 0 (EQ. 30)
R 2 = ---------------------------------------------
If setting the output voltage to be equal to the reference
set voltage as shown in Figure 21, the design procedure
can be followed as presented. However, when setting the
F LC = ---------------------------
F CE = ---------------------------------
1
2 π ? L ? C
1
2 π ? C ? ESR
(EQ. 29)
output voltage via a resistor divider placed at the input of
the differential amplifier (as shown in Figure 6), in order
to compensate for the attenuation introduced by the
The compensation network consists of the error amplifier
(internal to the ISL8103) and the external R 1 -R 3 , C 1 -C 3
components. The goal of the compensation network is to
provide a closed loop transfer function with high 0dB crossing
frequency (F 0 ; typically 0.1 to 0.3 of F SW ) and adequate phase
margin (better than 45°). Phase margin is the difference
between the closed loop phase at F 0dB and +180°. The
equations that follow relate the compensation network’s poles,
resistor divider, the obtained R 2 value needs be
multiplied by a factor of (R P +R S )/R P . The remainder of
the calculations remain unchanged, as long as the
compensated R 2 value is used.
2. Calculate C 1 such that F Z1 is placed at a fraction of the F LC ,
at 0.1 to 0.75 of F LC (to adjust, change the 0.5 factor to
desired number). The higher the quality factor of the output
filter and/or the higher the ratio F CE /F LC , the lower the F Z1
frequency (to maximize phase boost at F LC ).
C 1 = -----------------------------------------------
zeros and gain to the components (R 1 , R 2 , R 3 , C 1 , C 2 , and
22
1
2 π ? R 2 ? 0.5 ? F LC
(EQ. 31)
FN9246.1
July 21, 2008
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ISL8103CRZ-T | 功能描述:IC REG CTRLR BUCK PWM VM 40-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:500kHz 占空比:100% 电源电压:8.2 V ~ 30 V 降压:无 升压:无 回扫:是 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:0°C ~ 70°C 封装/外壳:8-DIP（0.300"，7.62mm） 包装:管件 产品目录页面:1316 (CN2011-ZH PDF) |
| ISL8103EVAL1 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Three-Phase Buck PWM Controller with High Current Integrated MOSFET Drivers |
| ISL8103IRZ | 功能描述:IC REG CTRLR BUCK PWM VM 40-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:500kHz 占空比:100% 电源电压:8.2 V ~ 30 V 降压:无 升压:无 回扫:是 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:0°C ~ 70°C 封装/外壳:8-DIP（0.300"，7.62mm） 包装:管件 产品目录页面:1316 (CN2011-ZH PDF) |
| ISL8103IRZ-T | 功能描述:IC REG CTRLR BUCK PWM VM 40-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 标准包装:75 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:1MHz 占空比:81% 电源电压:4.3 V ~ 13.5 V 降压:是 升压:是 回扫:是 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:无 工作温度:0°C ~ 70°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 包装:管件 产品目录页面:1051 (CN2011-ZH PDF) 其它名称:296-2543-5 |
| ISL8104 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Synchronous Buck Pulse-Width Modulator (PWM) Controller |
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