参数资料
型号: ISL8103CRZ
厂商: Intersil
文件页数: 19/28页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM VM 40-QFN
标准包装: 50
PWM 型: 电压模式
输出数: 1
频率 - 最大: 1.5MHz
占空比: 66.6%
电源电压: 4.75 V ~ 12.6 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: 0°C ~ 70°C
封装/外壳: 40-VFQFN 裸露焊盘
包装: 管件
ISL8103
Package Power Dissipation
When choosing MOSFETs it is important to consider the
amount of power being dissipated in the integrated drivers
located in the controller. Since there are a total of three
PVCC
BOOT
C GD
D
drivers in the controller package, the total power dissipated
by all three drivers must be less than the maximum
allowable power dissipation for the QFN package.
R HI1
R LO1
UGATE
G
R G1
R GI1
C GS
C DS
Q1
Calculating the power dissipation in the drivers for a desired
application is critical to ensure safe operation. Exceeding the
maximum allowable power dissipation level will push the IC
beyond the maximum recommended operating junction
temperature of +125°C. The maximum allowable IC power
dissipation for the 6x6 QFN package is approximately 4W at
room temperature. See “Layout Considerations” on page 25
for thermal transfer improvement suggestions.
S
PHASE
FIGURE 15. TYPICAL UPPER-GATE DRIVE TURN-ON PATH
PVCC
D
When designing the ISL8103 into an application, it is
recommended that the following calculation is used to
R HI2
LGATE
G
C GD
C DS
ensure safe operation at the desired frequency for the
selected MOSFETs. The total gate drive power losses,
P Qg_TOT , due to the gate charge of MOSFETs and the
integrated driver ’s internal circuitry and their corresponding
R LO2
R G2
R GI2
C GS
S
Q2
average driver current can be estimated with Equations 20
and 21, respectively.
P Qg_TOT = P Qg_Q1 + P Qg_Q2 + I Q ? VCC
FIGURE 16. TYPICAL LOWER-GATE DRIVE TURN-ON PATH
The total gate drive power losses are dissipated among the
P Qg_Q1 = --- ? Q G1 ? PVCC ? F SW ? N Q1 ? N PHASE
3
2
P Qg_Q2 = Q G2 ? PVCC ? F SW ? N Q2 ? N PHASE
(EQ. 20)
resistive components along the transition path and in the
bootstrap diode. The portion of the total power dissipated in
the controller itself is the power dissipated in the upper drive
path resistance, P DR_UP , the lower drive path resistance,
P DR_UP , and in the boot strap diode, P BOOT . The rest of the
power will be dissipated by the external gate resistors (R G1
I DR = ? --- ? Q G1 ? N
3
? 2
Q1
(EQ. 21)
?
+ Q G2 ? N Q2 ? ? N PHASE ? F SW + I Q
and R G2 ) and the internal gate resistors (R GI1 and R GI2 ) of
the MOSFETs. Figures 15 and 16 show the typical upper
and lower gate drives turn-on transition path. The total power
dissipation in the controller itself, P DR , can be roughly
P BOOT = ---------------------
In Equations 20 and 21, P Qg_Q1 is the total upper gate drive
power loss and P Qg_Q2 is the total lower gate drive power
loss; the gate charge (Q G1 and Q G2 ) is defined at the
particular gate to source drive voltage PVCC in the
corresponding MOSFET data sheet; I Q is the driver total
quiescent current with no load at both drive outputs; N Q1
and N Q2 are the number of upper and lower MOSFETs per
estimated as shown in Equation 22.
P DR = P DR_UP + P DR_LOW + P BOOT + ( I Q ? VCC )
P Qg_Q1
3
P DR_UP = ? -------------------------------------- + ---------------------------------------- ? ? ---------------------
? R HI1 + R EXT1 R LO1 + R EXT1 ?
phase, respectively; N PHASE is the number of active
phases. The I Q* VCC product is the quiescent power of the
controller without capacitive load and is typically 75mW at
? R HI1 R LO1 ? P Qg_Q1
3
(EQ. 22)
P DR_LOW = ? ? ? ---------------------
? R HI2 + R EXT2 R LO2 + R EXT2 ?
300kHz.
? R HI2 R LO2 ? P Qg_Q2
-------------------------------------- + ----------------------------------------
2
R EXT1 = R G1 + -------------
N
R EXT2 = R G2 + -------------
N
19
R GI1
Q1
R GI2
Q2
FN9246.1
July 21, 2008
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