参数资料
型号: ISL8103IRZ
厂商: Intersil
文件页数: 11/28页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM VM 40-QFN
标准包装: 50
PWM 型: 电压模式
输出数: 1
频率 - 最大: 1.5MHz
占空比: 66.6%
电源电压: 4.75 V ~ 12.6 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 85°C
封装/外壳: 40-VFQFN 裸露焊盘
包装: 管件
ISL8103
V COMP
+
-
+
-
PWM1
TO GATE
CONTROL
LOGIC
each channel in the converter, but may not be active
depending on the status of the PVCC3 and PVCC2 pins, as
described in the “PWM Operation” on page 10.
FILTER
f(s)
SAWTOOTH SIGNAL
DS ( ON )
I ER
+
-
I AVG
÷ N
Σ
I 3
I 2
I n
I
r
R
SEN = I L x --------------------------
ISEN
V IN
CHANNEL N
UPPER MOSFET
I 1
NOTE: Channel 2 and 3 are optional.
FIGURE 3. CHANNEL 1 PWM FUNCTION AND CURRENT-
BALANCE ADJUSTMENT
Current Sampling
SAMPLE
&
HOLD
-
+
ISEN(n)
R ISEN
CHANNEL N
I L
-
I L x r DS ( ON )
+
In order to realize proper current balance, the currents in
LOWER MOSFET
each channel must be sampled every switching cycle. This
sampling occurs during the forced off-time, following a PWM
ISL8103 INTERNAL CIRCUIT
EXTERNAL CIRCUIT
transition low. During this time the current sense amplifier
uses the ISEN inputs to reproduce a signal proportional to
the inductor current, I L . This sensed current, I SEN , is simply
a scaled version of the inductor current. The sample window
opens exactly 1/6 of the switching period, t SW , after the
PWM transitions low. The sample window then stays open
the rest of the switching cycle until PWM transitions high
again, as illustrated in Figure 4.
The sampled current, at the end of the t SAMPLE , is
proportional to the inductor current and is held until the next
switching period sample. The sampled current is used only
for channel current balance.
FIGURE 5. ISL8103 INTERNAL AND EXTERNAL CURRENT-
SENSING CIRCUITRY FOR CURRENT BALANCE
The ISL8103 senses the channel load current by sampling
the voltage across the lower MOSFET r DS(ON) , as shown in
Figure 5. A ground-referenced operational amplifier, internal
to the ISL8103, is connected to the PHASE node through a
resistor, R ISEN . The voltage across R ISEN is equivalent to
the voltage drop across the r DS(ON) of the lower MOSFET
while it is conducting. The resulting current into the ISEN pin
is proportional to the channel current, I L . The ISEN current is
sampled and held as described in “Current Sampling” on
page 11. From Figure 5, the following equation for I n is
derived where I L is the channel current.
I n = I L ? ----------------------
I L
r DS ( ON )
R ISEN
Output Voltage Setting
(EQ. 3)
PWM
SWITCHING PERIOD
I SEN
SAMPLING PERIOD
The ISL8103 uses a digital to analog converter (DAC) to
generate a reference voltage based on the logic signals at
the REF1, REF0 pins. The DAC decodes the 2-bit logic
signals into one of the discrete voltages shown in Table 1 on
page 12. Each REF0 and REF1 pins are pulled up to an
internal 1.2V voltage by weak current sources (40μA current,
decreasing to 0 as the voltage at the REF0, REF1 pins
varies from 0 to the internal 1.2V pull-up voltage). External
pull-up resistors or active-high output stages can augment
the pull-up current sources, up to a voltage of 5V. The DAC
OLD SAMPLE
CURRENT
TIME
NEW SAMPLE
CURRENT
pin must be connected to REF pin through a 1k Ω to 5k Ω
resistor and a filter capacitor (0.022μF) is connected
between REF and GND.
FIGURE 4. SAMPLE AND HOLD TIMING
The ISL8103 accommodates the use of external voltage
The ISL8103 supports MOSFET r DS(ON) current sensing to
sample each channel’s current for channel current balance.
The internal circuitry, shown in Figure 5 represents Channel
N of an N-channel converter. This circuitry is repeated for
11
reference connected to REF pin if a different output voltage
is required. The DAC voltage must be set at least as high as
the external reference. The error amp internal noninverting
input is the lower of REF or (DAC +300mV).
FN9246.1
July 21, 2008
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