参数资料
型号: ISL8103IRZ
厂商: Intersil
文件页数: 18/28页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM VM 40-QFN
标准包装: 50
PWM 型: 电压模式
输出数: 1
频率 - 最大: 1.5MHz
占空比: 66.6%
电源电压: 4.75 V ~ 12.6 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 85°C
封装/外壳: 40-VFQFN 裸露焊盘
包装: 管件
ISL8103
P LOW , 2 = V D ( ON ) ? F SW ? ? ------ + --------- ? ? t d1 + ? ------ – --------- ? ? t d2
I M
I PP
P UP , 1 ≈ V IN ? ? ------ + --------- ?
? ? ---- 1 ? ? F SW
? t ?
? N
2 ?
General Design Guide
This design guide is intended to provide a high-level
explanation of the steps necessary to create a multiphase
power converter. It is assumed that the reader is familiar with
many of the basic skills and techniques referenced below. In
addition to this guide, Intersil provides complete reference
designs that include schematics, bills of materials, and
example board layouts for many applications.
Power Stages
The first step in designing a mulitphase converter is to
determine the number of phases. This determination
depends heavily on the cost analysis which in turn depends
on system constraints that differ from one design to the next.
Principally, the designer will be concerned with whether
components can be mounted on both sides of the circuit
board, whether through-hole components are permitted, the
total board space available for power-supply circuitry, and
the maximum amount of load current. Generally speaking,
the most economical solutions are those in which each
phase handles between 25A and 30A. All surface-mount
designs will tend toward the lower end of this current range.
If through-hole MOSFETs and inductors can be used, higher
per-phase currents are possible. In cases where board
space is the limiting constraint, current can be pushed as
high as 40A per phase, but these designs require heat sinks
and forced air to cool the MOSFETs, inductors and
heat-dissipating surfaces.
MOSFETs
The choice of MOSFETs depends on the current each
MOSFET will be required to conduct, the switching frequency,
the capability of the MOSFETs to dissipate heat, and the
I M I PP I M I PP
? N 2 ? ? N 2 ?
(EQ. 15)
The total maximum power dissipated in each lower MOSFET
is approximated by the summation of P LOW,1 and P LOW,2 .
UPPER MOSFET POWER CALCULATION
In addition to r DS(ON) losses, a large portion of the
upper-MOSFET losses are due to currents conducted
across the input voltage (V IN ) during switching. Since a
substantially higher portion of the upper-MOSFET losses are
dependent on switching frequency, the power calculation is
more complex. Upper MOSFET losses can be divided into
separate components involving the upper-MOSFET
switching times, the lower-MOSFET body-diode
reverse-recovery charge, Q rr , and the upper MOSFET
r DS(ON) conduction loss.
When the upper MOSFET turns off, the lower MOSFET does
not conduct any portion of the inductor current until the
voltage at the phase node falls below ground. Once the
lower MOSFET begins conducting, the current in the upper
MOSFET falls to zero as the current in the lower MOSFET
ramps up to assume the full inductor current. In Equation 16,
the required time for this commutation is t 1 and the
approximated associated power loss is P UP,1 .
(EQ. 16)
? 2 ?
At turn on, the upper MOSFET begins to conduct and this
transition occurs over a time t 2 . In Equation 17, the
approximate power loss is P UP,2 .
P UP , 2 ≈ V IN ? ? ------ – ------------- P - ? ? ? ---- 2 ? ? F SW
availability and nature of heat sinking and air flow.
LOWER MOSFET POWER CALCULATION
? I M I P – ? ? t ?
? N 2 ? ? 2 ?
(EQ. 17)
· ? I M ? 2 I L , P – P ? ( 1 – d ) (EQ. 14)
P LOW , 1 = r DS ( ON ) ? ? ------ ? ? ( 1 – d ) + -----------------------------------------
P UP , 3 = V IN ? Q rr ? F SW
The calculation for the approximate power loss in the lower
MOSFET can be simplified, since virtually all of the loss in
the lower MOSFET is due to current conducted through the
channel resistance (r DS(ON) ). In Equation 14, I M is the
maximum continuous output current, I PP is the peak-to-peak
inductor current (see Equation 1), and d is the duty cycle
(V OUT /V IN ).
? N ? 12
An additional term can be added to the lower-MOSFET loss
A third component involves the lower MOSFET
reverse-recovery charge, Q rr . Since the inductor current has
fully commutated to the upper MOSFET before the lower-
MOSFET body diode can recover all of Q rr , it is conducted
through the upper MOSFET across V IN . The power
dissipated as a result is P UP,3 .
(EQ. 18)
Finally, the resistive part of the upper MOSFET is given in
Equation 19 as P UP,4 .
I P – 2
? I M ?
P UP , 4 ≈ r DS ( ON ) ? d ? ? ------ ? + ------------- P -
equation to account for additional loss accrued during the
dead time when inductor current is flowing through the
lower-MOSFET body diode. This term is dependent on the
? N ? 12
2
(EQ. 19)
diode forward voltage at I M , V D(ON) , the switching
frequency, F SW , and the length of dead times, t d1 and t d2 , at
the beginning and the end of the lower-MOSFET conduction
interval respectively.
18
The total power dissipated by the upper MOSFET at full load
can now be approximated as the summation of the results
from Equations 16, 17, 18 and 19. Since the power
equations depend on MOSFET parameters, choosing the
correct MOSFETs can be an iterative process involving
repetitive solutions to the loss equations for different
MOSFETs and different switching frequencies.
FN9246.1
July 21, 2008
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