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参数资料
| 型号： | ISL8105AIRZ-T |
| 厂商： | Intersil |
| 文件页数： | 11/16页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM VM 10-DFN |
| 标准包装： | 6,000 |
| PWM 型： | 电压模式 |
| 输出数： | 1 |
| 频率 - 最大： | 660kHz |
| 占空比： | 100% |
| 电源电压： | 6.5 V ~ 14.4 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 10-VFDFN 裸露焊盘 |
| 包装： | 带卷 (TR) |
ISL8105, ISL8105A
BOOT
+V IN
C 2
ISL8105
C BOOT
LX
Q1
L O
V OUT
COMP
R 2
C 1
R 3
C 3
+V BIAS
Q2
C O
-
BGATE/BSOC
V BIAS
C VBIAS
E/A
+
FB
R 1
GND
GND
VREF
FIGURE 8. PRINTED CIRCUIT BOARD SMALL SIGNAL
LAYOUT GUIDELINES
Minimize the loop from any pulldown transistor connected to
OSCILLATOR
V IN
V OUT
COMP/EN pin to reduce antenna effect. Provide local
decoupling between VBIAS and GND pins as described
PWM
CIRCUIT
V OSC
earlier. Locate the capacitor, C BOOT , as close as practical to
the BOOT and LX pins. All components used for feedback
compensation (not shown) should be located as close to the
IC as practical.
Feedback Compensation
HALF-BRIDGE
DRIVE
TGATE
LX
BGATE
L
DCR
C
ESR
This section highlights the design considerations for a
voltage-mode controller requiring external compensation. To
address a broad range of applications, a type-3 feedback
ISL8105
EXTERNAL CIRCUIT
network is recommended (see Figure 9).
Figure 9 highlights the voltage-mode control loop for a
synchronous-rectified buck converter, applicable to the
ISL8105 circuit. The output voltage (V OUT ) is regulated to
the reference voltage, V REF , level. The error amplifier output
(COMP pin voltage) is compared with the oscillator (OSC)
triangle wave to provide a pulse-width modulated wave with
an amplitude of V IN at the LX node. The PWM wave is
smoothed by the output filter (L and C). The output filter
capacitor bank’s equivalent series resistance is represented
by the series resistor ESR.
FIGURE 9. VOLTAGE-MODE BUCK CONVERTER
COMPENSATION DESIGN
Equations 5 through 8 that relate the compensation network’s
poles, zeros and gain to the components (R 1 , R 2 , R 3 , C 1 , C 2 ,
and C 3 ) in Figure 9. Use the following guidelines for locating
the poles and zeros of the compensation network:
1. Select a value for R 1 (1k Ω to 10k Ω , typically). Calculate
value for R 2 for desired converter bandwidth (F 0 ). If
setting the output voltage to be equal to the reference set
voltage as shown in Figure 9, the design procedure can
be followed as presented in Equation 5.
d MAX ? V IN ? F LC
The modulator transfer function is the small-signal transfer
function of V OUT /V COMP . This function is dominated by a DC
gain, given by d MAX V IN /V OSC , and shaped by the output filter,
V OSC ? R 1 ? F 0
R 2 = ---------------------------------------------
(EQ. 5)
F LC = ---------------------------
F CE = ---------------------------------
C 1 = -----------------------------------------------
with a double pole break frequency at F LC and a zero at F CE .
For the purpose of this analysis, C and ESR represent the total
output capacitance and its equivalent series resistance.
1 1
2 π ? L ? C 2 π ? C ? ESR (EQ. 4)
The compensation network consists of the error amplifier
2. Calculate C 1 such that F Z1 is placed at a fraction of the F LC ,
at 0.1 to 0.75 of F LC (to adjust, change the 0.5 factor to
desired number). The higher the quality factor of the output
filter and/or the higher the ratio F CE /F LC , the lower the F Z1
frequency (to maximize phase boost at F LC ).
1
2 π ? R 2 ? 0.5 ? F LC (EQ. 6)
2 π ? R 2 ? C 1 ? F CE – 1
(internal to the ISL8105) and the external R 1 to R 3 , C 1 to C 3
components. The goal of the compensation network is to
provide a closed loop transfer function with high 0dB crossing
frequency (F 0 ; typically 0.1 to 0.3 of f SW ) and adequate phase
3. Calculate C 2 such that F P1 is placed at F CE .
C 1
C 2 = --------------------------------------------------------
(EQ. 7)
margin (better than +45°).
Phase margin is the difference between the closed loop
phase at F 0dB and +180°.
11
4. Calculate R 3 such that F Z2 is placed at F LC . Calculate C 3
such that F P2 is placed below f SW (typically, 0.5 to 1.0
times f SW ). f SW represents the regulator ’s switching
frequency. Change the numerical factor to reflect desired
placement of this pole. Placement of F P2 lower in
FN6306.5
April 15, 2010
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相关代理商/技术参数 |
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| ISL8105B | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:+5V or +12V Single-Phase Synchronous Buck Converter PWM Controller with Integrated MOSFET Gate Drivers, Extended Soft-Start Time |
| ISL8105BCBZ | 功能描述:IC REG CTRLR BUCK PWM VM 8-SOIC RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:275kHz 占空比:50% 电源电压:18 V ~ 110 V 降压:无 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 包装:带卷 (TR) |
| ISL8105BCBZ-T | 功能描述:IC REG CTRLR BUCK PWM VM 8-SOIC RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 标准包装:4,500 系列:PowerWise® PWM 型:控制器 输出数:1 频率 - 最大:1MHz 占空比:95% 电源电压:2.8 V ~ 5.5 V 降压:是 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:无 工作温度:-40°C ~ 125°C 封装/外壳:6-WDFN 裸露焊盘 包装:带卷 (TR) 配用:LM1771EVAL-ND - BOARD EVALUATION LM1771 其它名称:LM1771SSDX |
| ISL8105BCRZ | 功能描述:IC REG CTRLR BUCK PWM VM 10-DFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:275kHz 占空比:50% 电源电压:18 V ~ 110 V 降压:无 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 包装:带卷 (TR) |
| ISL8105BCRZ-T | 功能描述:IC REG CTRLR BUCK PWM VM 10-DFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 标准包装:4,500 系列:PowerWise® PWM 型:控制器 输出数:1 频率 - 最大:1MHz 占空比:95% 电源电压:2.8 V ~ 5.5 V 降压:是 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:无 工作温度:-40°C ~ 125°C 封装/外壳:6-WDFN 裸露焊盘 包装:带卷 (TR) 配用:LM1771EVAL-ND - BOARD EVALUATION LM1771 其它名称:LM1771SSDX |
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