参数资料
型号: ISL8105AIRZ-T
厂商: Intersil
文件页数: 7/16页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM VM 10-DFN
标准包装: 6,000
PWM 型: 电压模式
输出数: 1
频率 - 最大: 660kHz
占空比: 100%
电源电压: 6.5 V ~ 14.4 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 85°C
封装/外壳: 10-VFDFN 裸露焊盘
包装: 带卷 (TR)
ISL8105, ISL8105A
Overcurrent Protection (OCP)
The overcurrent function protects the converter from a
shorted output by using the bottom-side MOSFET's
V OUT OVER-CHARGED
V OUT PRE-BIASED
V
V OUT NORMAL
on-resistance, r DS(ON) , to monitor the current. A resistor
(R BSOC ) programs the overcurrent trip level (see “Typical
Application Diagram” on page 2). This method enhances the
converter's efficiency and reduces cost by eliminating a
current sensing resistor. If overcurrent is detected, the output
immediately shuts off, it cycles the soft-start function in a
hiccup mode (2 dummy soft-start time-outs, then up to one
real one) to provide fault protection. If the shorted condition
t0
t1 t1
t2
is not removed, this cycle will continue indefinitely.
Following POR (and 6.8ms delay), the ISL8105, ISL8105A
initiates the Overcurrent Protection sample and hold
FIGURE 3. SOFT-START WITH PRE-BIAS
to 10.2ms for the delay and OCP sample and 6.8ms for the
soft-start ramp.
Figure 3 shows the normal curve in blue; initialization begins
at t 0 , and the output ramps between t 1 and t 2 . If the output is
pre-biased to a voltage less than the expected value, as
shown by the red curve, the ISL8105, ISL8105A will detect
that condition. Neither MOSFET will turn on until the
soft-start ramp voltage exceeds the output; V OUT starts
seamlessly ramping from there. If the output is pre-biased to
a voltage above the expected value, as in the gray curve,
neither MOSFET will turn on until the end of the soft-start, at
which time it will pull the output voltage down to the final
value. Any resistive load connected to the output will help
pull down the voltage (at the RC rate of the R of the load and
the C of the output capacitance).
If the V IN for the synchronous buck converter is from a
different supply that comes up after V BIAS , the soft-start
would go through its cycle, but with no output voltage ramp.
When V IN turns on, the output would follow the ramp of the
V IN from zero up to the final expected voltage (at close to
100% duty cycle, with COMP/EN pin >4V). If V IN is too fast,
there may be excessive inrush current charging the output
capacitors (only the beginning of the ramp, from zero to
V OUT matters here). If this is not acceptable, then consider
changing the sequencing of the power supplies, or sharing
the same supply, or adding sequencing logic to the
COMP/EN pin to delay the soft-start until the V IN supply is
ready (see “Input Voltage Considerations” on page 9).
If the IC is disabled after soft-start (by pulling COMP/EN pin
low), and then enabled (by releasing the COMP/EN pin),
then the full initialization (including OCP sample) will take
place. However, there is no new OCP sampling during
overcurrent retries. If the output is shorted to GND during
soft-start, the OCP will handle it, as described in the next
section.
If the output is shorted to GND during soft-start, the OCP will
handle it, as described in the next section.
7
operation. The BGATE driver is disabled to allow an internal
21.5μA current source to develop a voltage across R BSOC .
The ISL8105, ISL8105A samples this voltage (which is
referenced to the GND pin) at the BGATE/BSOC pin, and
holds it in a counter and DAC combination. This sampled
voltage is held internally as the Overcurrent Set Point, for as
long as power is applied, or until a new sample is taken after
coming out of a shut-down.
The actual monitoring of the bottom-side MOSFET's
on-resistance starts 200ns (nominal) after the edge of the
internal PWM logic signal (that creates the rising external
BGATE signal). This is done to allow the gate transition
noise and ringing on the LX pin to settle out before
monitoring. The monitoring ends when the internal PWM
edge (and thus BGATE) goes low. The OCP can be detected
anywhere within the above window.
If the regulator is running at high TGATE duty cycles (around
75% for 600kHz or 87% for 300kHz operation), then the
BGATE pulse width may not be wide enough for the OCP to
properly sample the r DS(ON) . For those cases, if the BGATE
is too narrow (or not there at all) for 3 consecutive pulses,
then the third pulse will be stretched and/or inserted to the
425ns minimum width. This allows for OCP monitoring every
third pulse under this condition. This can introduce a small
pulse-width error on the output voltage, which will be
corrected on the next pulse; and the output ripple voltage will
have an unusual 3-clock pattern, which may look like jitter. If
the OCP is disabled (by choosing a too-high value of
R BSOC , or no resistor at all), then the pulse stretching
feature is also disabled. Figure 4 illustrates the BGATE pulse
width stretching, as the width gets smaller.
FN6306.5
April 15, 2010
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