参数资料
型号: ISL8105AIRZ-T
厂商: Intersil
文件页数: 14/16页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM VM 10-DFN
标准包装: 6,000
PWM 型: 电压模式
输出数: 1
频率 - 最大: 660kHz
占空比: 100%
电源电压: 6.5 V ~ 14.4 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 85°C
封装/外壳: 10-VFDFN 裸露焊盘
包装: 带卷 (TR)
ISL8105, ISL8105A
components: conduction loss and switching loss. The
conduction losses are the largest component of power
dissipation for both the top and the bottom-side MOSFETs.
These losses are distributed between the two MOSFETs
according to duty factor. The switching losses seen when
sourcing current will be different from the switching losses
seen when sinking current. When sourcing current, the
top-side MOSFET realizes most of the switching losses. The
bottom-side switch realizes most of the switching losses
when the converter is sinking current (see Equation 14).
These equations assume linear voltage current transitions
and do not adequately model power loss due to the reverse
recovery of the upper and lower MOSFET’s body diode. The
gate-charge losses are dissipated by the ISL8105 and do not
complementary MOSFET is turned on. Also avoid MOSFETs
with excessive switching times; the circuitry is expecting
transitions to occur in under 50ns or so.
Bootstrap Considerations
Figure 12 shows the top-side gate drive (BOOT pin) supplied
by a bootstrap circuit from V BIAS . The boot capacitor,
C BOOT , develops a floating supply voltage referenced to the
LX pin. The supply is refreshed to a voltage of V BIAS less
the boot diode drop (V D ) each time the lower MOSFET, Q 2 ,
turns on. Check that the voltage rating of the capacitor is
above the maximum V BIAS voltage in the system. A 16V
rating should be sufficient for a 12V system. A value of 0.1μF
is typical for many systems driving single MOSFETs.
heat the MOSFETs. However, large gate charge increases
the switching interval, t SW , which increases the MOSFET
switching losses. Ensure that both MOSFETs are within their
maximum junction temperature at high ambient temperature
by calculating the temperature rise according to package
+V BIAS
+
V D
-
BOOT
+1V TO +12V
thermal-resistance specifications. A separate heatsink may
be necessary depending upon MOSFET power, package
type, ambient temperature and air flow.
ISL8105
TGATE
C BOOT
Q1
V G-S ≈ V BIAS - V D
LX
Losses while Sourcing Current
P TOP = Io × r DS ( ON ) × D + --- ? Io × V IN × t SW × f S
2 1
2
+V BIAS
P BOTTOM = Io 2 x r DS(ON) x (1 - D)
Losses while Sinking Current
-
+
BGATE
Q2
NOTE:
V G-S ≈ V BIAS
P TOP = Io 2 x r DS(ON) x D
P BOTTOM = Io × r DS ( ON ) × ( 1 – D ) + --- ? Io × V IN × t SW × f S
2 1
2
(EQ. 14)
Where:
D is the duty cycle = V OUT / V IN ,
t SW is the combined switch ON and OFF time, and
f S is the switching frequency.
When operating with a 12V power supply for V BIAS (or down
to a minimum supply voltage of 6.5V), a wide variety of
NMOSFETs can be used. Check the absolute maximum
V GS rating for both MOSFETs; it needs to be above the
highest V BIAS voltage allowed in the system; that usually
means a 20V V GS rating (which typically correlates with a
30V V DS maximum rating). Low threshold transistors
(around 1V or below) are not recommended for the reasons
explained in the next paragraph.
For 5V-only operation, given the reduced available gate bias
voltage (5V), logic-level transistors should be used for both
N-MOSFETs. Look for r DS(ON) ratings at 4.5V. Caution
should be exercised with devices exhibiting very low
V GS(ON) characteristics. The shoot-through protection
present aboard the ISL8105 may be circumvented by these
MOSFETs if they have large parasitic impedances and/or
capacitances that would inhibit the gate of the MOSFET from
being discharged below its threshold level before the
14
GND
FIGURE 12. UPPER GATE DRIVE - BOOTSTRAP OPTION
If V BIAS is 12V, but V IN is lower (such as 5V), then another
option is to connect the BOOT pin to 12V and remove the
BOOT capacitor (although, you may want to add a local
capacitor from BOOT to GND). This will make the TGATE
V GS voltage equal to (12V - 5V = 7V). That should be high
enough to drive most MOSFETs, and low enough to improve
the efficiency slightly. Do NOT leave the BOOT pin open,
and try to get the same effect by driving BOOT through
V BIAS and the internal diode; this path is not designed for
the high current pulses that will result.
For low V BIAS voltage applications where efficiency is very
important, an external BOOT diode (in parallel with the
internal one) may be considered. The external diode drop
has to be lower than the internal one. The resulting higher
V G-S of the top-side FET will lower its r DS(ON) . The modest
gain in efficiency should be balanced against the extra cost
and area of the external diode.
For information on the Application circuit, including a
complete Bill-of-Materials and circuit board description, can
be found in Application Note AN1258.
http://www.intersil.com/data/an/AN1258.pdf
FN6306.5
April 15, 2010
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