参数资料
型号: ISL8106IRZ
厂商: Intersil
文件页数: 10/15页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM VM 16-QFN
标准包装: 75
系列: Robust Ripple Regulator™ (R³)
PWM 型: 电压模式
输出数: 1
频率 - 最大: 600kHz
电源电压: 7 V ~ 25 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 85°C
封装/外壳: 16-VQFN 裸露焊盘
包装: 管件
ISL8106
Where:
- R BSOC ( Ω ) is the resistor used to program the over-
current setpoint
- I BSOC is the current sense current that is sourced from
the BSOC pin
- I OC is the I BSOC threshold current value sourced from
the BSOC pin that will activate the OCP circuit
- I FL is the maximum continuous DC load current
- I PP is the inductor peak-to-peak ripple current
- OC SP is the desired overcurrent setpoint expressed as
a multiplier relative to I FL
Overvoltage
When an OVP fault is detected, the ISL8106 overvoltage
protection circuit will pull the PGOOD pin low and latch off
the converter. The fault will remain latched until the EN pin is
pulled below V ENF or if the voltage at the VIN pin is reduced
to the extent that V CC has fallen below the POR V CCF
threshold.
When the voltage at the FB pin (relative to the GND pin) has
exceeded the rising overvoltage threshold V OVR , the
converter will latch off; however, the BGATE driver output will
stay high, forcing the bottom-side MOSFET to pull down the
output voltage of the converter. The bottom-side MOSFET
will continue to pull down the output voltage until the voltage
low. If the EN pin is pulled below V ENF or if the voltage at the
VIN is reduced to the extent that V CC has fallen below the
POR V CCF threshold, normal operation will resume
however, the temperature hysteresis T OTHYS is reset.
Application Guidelines
Layout Considerations
As in any high frequency switching converter, layout is very
important. Switching current from one power device to
another can generate voltage transients across the
impedances of the interconnecting bond wires and circuit
traces. These interconnecting impedances should be
minimized by using wide, short printed circuit traces. The
critical components should be located as close together as
possible using ground plane construction or single point
grounding.
A multi-layer printed circuit board is recommended. Figure 4
shows the critical components of the converter. Note that
capacitors C IN and C OUT could each represent numerous
physical capacitors. Dedicate one solid layer, usually a
middle layer of the PC board, for a ground plane and make
all critical component ground connections with vias to this
layer. Dedicate another solid layer as a power plane and
break this plane into smaller islands of common voltage
at the FB pin relative to the GND pin, has decayed below the
falling overvoltage threshold V OVF, at which time the BGATE
driver output is driven low, forcing the bottom-side MOSFET
off. The BGATE driver output will continue to switch on at
V OVR and switch off at V OVF until the EN pin is pulled below
V ENF or if the voltage at the VIN is reduced to the extent that
V CC has fallen below the POR V CCF threshold.
VCC
PVCC
ISL8106
C BP_PVCC
C BP_VCC
R VCC
VIN
UnderVoltage
When an UVP fault is detected, the ISL8106 undervoltage
protection circuit will pull the PGOOD pin low and latch off
TGATE
BOOT
Q 1
C IN
the converter. The UVP fault occurs when the voltage at the
FB pin relative to the GND pin, has fallen below the under-
LX
C IN
L OUT
V OUT
voltage threshold V UV. The fault will remain latched until the
EN pin is pulled below V ENF or if the voltage at the VIN is
C OUT
reduced to the extent that V CC has fallen below the POR
V CCF threshold.
Over-Temperature
When an OTP fault is detected, the ISL8106 over-
temperature protection circuit suspends PWM, but will not
BGATE
PGND
GND
Q 2
affect the PGOOD pin, or latch off the converter. The over-
temperature protection circuit measures the temperature of
the silicon and activates when the rising threshold
temperature T OTR has been exceeded. The PWM remains
suspended until the silicon temperature falls below the
temperature hysteresis T OTHYS at which time normal
operation is resumed. All other protection circuits will
function normally during OTP however, since PWM is
inhibited, it is likely that the converter will immediately
experience an undervoltage fault, latch off, and pull PGOOD
10
KEY
TRACE SIZED FOR 4A PEAK CURRENT
SHORT TRACE, MINIMUM IMPEDANCE
ISLAND ON POWER PLANE LAYER
ISLAND ON CIRCUIT AND/OR POWER PLANE LAYER
VIA CONNECTION TO GROUND PLANE
FIGURE 4. PRINTED CIRCUIT BOARD POWER PLANES
AND ISLANDS
FN9283.1
November 10, 2006
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