参数资料
型号: ISL8106IRZ
厂商: Intersil
文件页数: 12/15页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM VM 16-QFN
标准包装: 75
系列: Robust Ripple Regulator™ (R³)
PWM 型: 电压模式
输出数: 1
频率 - 最大: 600kHz
电源电压: 7 V ~ 25 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 85°C
封装/外壳: 16-VQFN 裸露焊盘
包装: 管件
ISL8106
paralleled to adjust the ESR to achieve the required V PP .
The inductance of the capacitor can cause a brief voltage dip
when the load transient has an extremely high slew rate.
Low inductance capacitors constructed with reverse
package geometry are available.
A capacitor dissipates heat as a function of RMS current. Be
sure that I PP is shared by a sufficient quantity of paralleled
capacitors so that they operate below the maximum rated
RMS current. Take into account that the specified value of a
capacitor can drop as much as 50% as the DC voltage
across it increases.
Selection of the Input Capacitor
The important parameters for the bulk input capacitance are
the voltage rating and the RMS current rating. For reliable
operation, select bulk capacitors with voltage and current
ratings above the maximum input voltage and capable of
supplying the RMS current required by the switching circuit.
Their voltage rating should be at least 1.25 times greater
than the maximum input voltage, while a voltage rating of 1.5
times is a preferred rating. Figure 5 is a graph of the input
RMS ripple current, normalized relative to output load current,
as a function of duty cycle that is adjusted for converter
efficiency. The ripple current calculation is written as:
In addition to the bulk capacitance, some low ESL ceramic
capacitance is recommended to decouple between the drain
terminal of the top-side MOSFET and the source terminal of
the bottom-side MOSFET, in order to reduce the voltage
ringing created by the switching current across parasitic
circuit elements.
MOSFET Selection and Considerations
Typically, MOSFETS cannot tolerate even brief excursions
beyond their maximum drain to source voltage rating. The
MOSFETS used in the power conversion stage of the
converter should have a maximum V DS rating that exceeds
the upper voltage tolerance of the input power source, and
the voltage spike that occurs when the MOSFET switches
off. Placing a low ESR ceramic capacitor as close as
practical across the drain of the top-side MOSFET and the
source of the bottom-side MOSFET will reduce the
amplitude of the turn-off voltage spike.
The MOSFET input capacitance C ISS, and on-state drain to
source resistance r DS(ON) , are to an extent, inversely
related; reduction of r DS(ON) typically results in an increase
of C ISS . These two parameters affect the efficiency of the
converter in different ways. The r DS(ON) affects the power
loss when the MOSFET is completely turned on and
( I MAX ? ( D – D ) ) + ? x ? I MAX ? ------ ?
2 2 2 D
? 12 ?
I IN_RMS = -----------------------------------------------------------------------------------------------------
I MAX
(EQ. 14)
conducting current. The C ISS affects the power loss when
the MOSFET is actively switching. Switching time increases
as C ISS increases. When the MOSFET switches it will briefly
conduct current while the drain to source voltage is still
V OUT
V IN ? EFF
Where:
- I MAX is the maximum continuous I LOAD of the converter
- x is a multiplier (0 to 1) corresponding to the inductor
peak-to-peak ripple amplitude expressed as a
percentage of I MAX (0% to 100%)
- D is the duty cycle that is adjusted to take into account
the efficiency of the converter which is written as:
D = --------------------------
0.6
0.55
0.5
0.45
0.4
0.35
0.3
present. The power dissipation during this time is substantial
so it must be kept as short as practical. Often the top-side
MOSFET and the bottom-side MOSFET are different
devices due to the trade-offs that have to be made between
C ISS and r DS(ON) .
The bottom-side MOSFET power loss is dominated by
r DS(ON) because it conducts current for the majority of the
PWM switching cycle; the r DS(ON) should be small. The
switching loss is small for the bottom-side MOSFET even
though C ISS is large due to the low r DS(ON) of the device,
because the drain to source voltage is clamped by the body
diode. The top-side MOSFET power loss is dominated by
C ISS because it conducts current for the minority of the
PWM switching cycle; the C ISS should be small. The
switching loss of the top-side MOSFET is large compared to
the bottom-side MOSFET because the drain to source
voltage is not clamped. For the bottom-side MOSFET, its
power loss can be assumed to be the conduction loss only
P CONBS D ( V IN ) ≈ [ I LOAD ]
0.25
0.2
0.15
x=1
x = 0.75
x = 0.50
x = 0.25
x=0
and can be written as:
?
2
?
r DS ( ON ) BS ? [ 1 – D ( V IN ) ]
(EQ. 15)
0.1
0.05
For the top-side MOSFET, its conduction loss can be written
as:
P CONTS D ( V IN ) = [ I LOAD ]
0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
?
2
?
r DS ( ON ) TS ? D ( V IN )
(EQ. 16)
DUTY CYCLE
FIGURE 5. NORMALIZED RMS INPUT CURRENT FOR x = 0.8
12
FN9283.1
November 10, 2006
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