参数资料
型号: ISL8106IRZ
厂商: Intersil
文件页数: 7/15页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM VM 16-QFN
标准包装: 75
系列: Robust Ripple Regulator™ (R³)
PWM 型: 电压模式
输出数: 1
频率 - 最大: 600kHz
电源电压: 7 V ~ 25 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 85°C
封装/外壳: 16-VQFN 裸露焊盘
包装: 管件
ISL8106
PGND (Pin 10)
The PGND pin should be connected to the source of the
bottom-side MOSFET, preferably with an isolated path that is
in parallel with the trace connecting the BGATE pin to the
gate of the MOSFET. The PGND pin is an isolated path used
exclusively to conduct the turn-off transient current that flows
out the PGND pin, through the gate-source capacitance of
the bottom-side MOSFET, into the BGATE pin, and back to
the PGND pin through the pull-down resistance of the
BGATE driver. The adaptive shoot-through protection circuit,
measures the bottom-side MOSFET gate voltage with
respect to the PGND pin, not the GND pin.
BGATE (Pin 11)
The BGATE pin is the output of the bottom-side MOSFET
gate driver. Connect to the gate of the bottom-side MOSFET.
The signal going through this trace is both high dv/dt and
high di/dt, with high peak charging and discharging current.
Route this trace in parallel with the trace from the PGND pin.
These two traces should be short, wide, and away from
other traces. There should be no other weak signal traces in
parallel with these traces on any layer.
PVCC (Pin 12)
The PVCC pin is the input voltage for the bottom-side
MOSFET gate driver BGATE. Connect a +5V power source
to the PVCC pin with respect to the GND pin, a 1μF MLCC
bypass capacitor needs to be connected from the PVCC pin
to the PGND pin, not the GND pin. The VCC output may be
used for the PVCC input voltage source. Connect the VCC
pin to the PVCC pin through a low-pass filter consisting of a
resistor and the PVCC bypass capacitor. Refer to Typical
Application Schematic .
BOOT (Pin 13)
The BOOT pin stores the input voltage for the top-side
MOSFET gate driver. Connect an MLCC capacitor across
the BOOT and LX pins. The boot capacitor is charged
through an internal boot diode connected from the PVCC pin
to the BOOT pin, each time the LX pin drops below PVCC
minus the voltage dropped across the internal boot diode.
TGATE (Pin 14)
The TGATE pin is the output of the top-side MOSFET gate
driver. Connect to the gate of the top-side MOSFET.
The signal going through this trace is both high dv/dt and
high di/dt, with high peak charging and discharging current.
Route this trace in parallel with the trace from the LX pin.
These two traces should be short, wide, and away from
other traces. There should be no other weak signal traces in
parallel with these traces on any layer.
LX (Pin 15)
The LX pin is the return current path for the TGATE
MOSFET driver. The LX pin also measures the polarity of
7
the bottom-side MOSFET drain voltage for the diode
emulation function.
Connect the LX pin to the node consisting of the top-side
MOSFET source, the bottom-side MOSFET drain, and the
output inductor. Refer to Typical Application Schematic . This
trace should be short, and positioned away from other weak
signal traces. The parasitic capacitance and parasitic
inductance of the LX node should be kept very low to
minimize ringing. If ringing is excessive, it could easily affect
current sample information. It would be best to limit the size
of the LX node copper in strict accordance with the current
and thermal management of the application.
PGOOD (Pin 16)
The PGOOD pin is an open-drain output that is high
impedance when the converter is in regulation, or when the
EN pin is pulled below the falling threshold voltage V ENTHF .
The PGOOD pin has three distinct pull-down impedances
that correspond to an OVP fault, OCP/SCP, or UVP and soft-
start. Connect the PGOOD pin to +5V through a pull-up
resistor.
Functional Description
POR and Soft-Start
The power-on reset (POR) circuit monitors V CC for the
V CCR (rising) and V CCF (falling) voltage thresholds. The
purpose of soft-start is to limit the inrush current through the
output capacitors when the converter first turns on. The
PWM soft-start sequence initializes once V CC rises above
the V CCR threshold, beginning from below the V CCF
threshold.
The ISL8106 uses a digital soft-start circuit to ramp the
output voltage of the converter to the programmed regulation
setpoint in approximately 1.5ms. The converter regulates to
600mV at the FB pin with respect to the GND pin. During
soft-start a digitally derived voltage reference forces the
converter to regulate from 0V to 600mV at the FB pin. When
the EN pin is pulled above the rising EN threshold voltage
V ENTHR the PGOOD Soft-Start Delay T SS begins and the
output voltage begins to rise. The output voltage enters
regulation in approximately 1.5ms and the PGOOD pin goes
to high impedance once T SS has elapsed.
When the EN pin is pulled below the V ENF threshold, the
LDO stops regulating and PWM immediately stops,
regardless of the falling V CC voltage. The soft-start
sequence can be reinitialized and fault latches reset, once
V CC falls below the V CCF threshold.
FN9283.1
November 10, 2006
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