参数资料
型号: ISL8106IRZ
厂商: Intersil
文件页数: 8/15页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM VM 16-QFN
标准包装: 75
系列: Robust Ripple Regulator™ (R³)
PWM 型: 电压模式
输出数: 1
频率 - 最大: 600kHz
电源电压: 7 V ~ 25 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 85°C
封装/外壳: 16-VQFN 裸露焊盘
包装: 管件
ISL8106
can simultaneously affect the PWM switching frequency and
PWM duty cycle in response to input voltage and output load
transients. The term “Ripple” in the name “Robust-Ripple-
Regulator” refers to the converter output inductor ripple
EN
V OUT
1.5ms
PGOOD
2.75ms
FIGURE 1. SOFT-START SEQUENCE
PGOOD
The PGOOD pin connects to three open drain MOSFETS
each of which has a different r DS(ON) . The PGOOD pin is an
undefined impedance if V CC has not reached the rising POR
threshold V CCR , or if V CC is below the falling POR threshold
current, not the converter output ripple voltage. The output
voltage is regulated to 600mV at the FB pin with respect to
the GND pin. The FB pin is the inverting input of the error
amplifier. The frequency response of the feedback control
loop is tuned with a type-two compensation network
connected across the FB pin and COMP pin.
The R 3 modulator synthesizes an AC signal V R , which is an
ideal representation of the output inductor ripple current. The
duty-cycle of V R is derived from the voltage measured at the
VIN pin and VO pin with respect to the GND pin.
Transconductance amplifiers convert the VIN and VO
voltages into currents that charge and discharge the ripple
capacitor C R . The positive slope of V R can be written as:
V RPOS = ( gm ) ? ( V IN – V O ) (EQ. 1)
The negative slope of V R can be written as:
V CCF . The ISL8106 features a unique fault-identification
capability that can drastically reduce trouble-shooting time
V RNEG = gm ? V O
(EQ. 2)
and effort. The pull-down resistance of the PGOOD pin
corresponds to the fault status of the controller. During soft-
start or if an undervoltage fault occurs, the PGOOD pulldown
resistance is 95 Ω , or 30 Ω for an overcurrent fault, or 60 Ω for
an overvoltage fault.
TABLE 1. PGOOD PULL-DOWN RESISTANCE
A voltage V W is referenced with respect to the error amplifier
output voltage V COMP , creating a window-voltage envelope
into which voltage V R is compared. The V R, V COMP, and V W
signals feed into a hysteretic window comparator in which
V COMP is the lower threshold voltage and V W is the higher
threshold voltage. PWM pulses are generated as V R
traverses the V W and V COMP thresholds. The charging and
LDO
CONDITION
IC Off
Soft-Start
Undervoltage Fault
Overvoltage Fault
Overcurrent Fault
PGOOD RESISTANCE
Open
95 Ω
95 Ω
60 Ω
30 Ω
discharging rates of capacitor C R determine the PWM
switching frequency for a given amplitude of V W with respect
to V COMP . The R 3 regulator simultaneously affects switching
frequency and duty cycle because it modulates both edges
of the PWM pulses.
Voltage applied to the VIN pin with respect to the GND pin is
regulated to +5VDC by an internal low-dropout voltage
regulator (LDO). The output of the LDO is called V CC , which
is the bias voltage used by the IC internal circuitry. The LDO
output is routed to the VCC pin and requires a ceramic
capacitor connected to the GND pin to stabilize the LDO and
to decouple load transients.
When the EN pin rises above the V ENR threshold, V CC will
turn on and rise to its regulation voltage. The LDO regulates
V CC by pulling up towards the voltage at the VIN pin; the
LDO has no pull-down capability.
Pulse Width Modulator
The ISL8106 is a hybrid of fixed frequency PWM control, and
Ripple Capacitor Voltage CR
Window Voltage VW
Error Amplifier Voltage VCOMP
PWM
variable frequency hysteretic control. Intersil’s R 3 technology
8
FIGURE 2. MODULATOR WAVEFORMS DURING LOAD
TRANSIENT
FN9283.1
November 10, 2006
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