参数资料
型号: ISL8126IRZ-TK
厂商: Intersil
文件页数: 33/39页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM VM 32-QFN
标准包装: 1,000
PWM 型: 电压模式
输出数: 2
频率 - 最大: 1.5MHz
占空比: 90%
电源电压: 3 V ~ 5.6 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 85°C
封装/外壳: 32-VFQFN 裸露焊盘
包装: 带卷 (TR)
ISL8126
I VIN = ? --------------------------- + --------------------------- ? ? PVCC ? F SW + I Q_VIN
P DR_UP = ? ----------------------------------- + ------------------------------------- ? ? -------------------
R HI1 + R EXT1 R LO1 + R EXT1 ?
?
P DR_LOW = ? ----------------------------------- + ------------------------------------- ? ? -------------------
R HI2 + R EXT2 R LO2 + R EXT2 ?
?
P IC = ( VIN – PVCC ) ? I VIN + P DR
? Q G1 ? N Q1 Q G2 ? N Q2 ?
? V GS1 V GS2 ?
P DR = P DR_UP + P DR_LOW
? R HI1 R LO1 ? P Qg_Q1
? R HI2 R LO2 ? P Qg_Q2
2
2
(EQ. 15)
(EQ. 16)
It is recommended that operating junction temperature of the IC
to be less that +135°C. This limits the maximum power
dissipation inside the IC. Equations 14, 16 and θ JA can be used to
estimate the maximum total gate change, Q g_total . The power
dissipation inside the IC should be evaluated at the maximum
ambient temperature. In addition, the total gate change and the
operating switching frequency should not load the internal LDO
beyond the current limit threshold. Figure 27 provides the
guideline of the allowed maximum gate charge.
0.27
0.24
0.21
Q G1 ? PVCC 2
P Qg_Q1 = ----------------------------------- ? F SW ? N Q1
Q G2 ? PVCC 2
P Qg_Q2 = ----------------------------------- ? F SW ? N Q2
V GS1
V GS2
R GI1 R GI2
N N
R EXT2 = R G1 + ------------ R EXT2 = R G2 + ------------
Q1 Q2
0.18
0.15
0.12
0.09
0.06
T A = +85°C
T A = +20°C
PVCC
BOOT
0.03
D
0.00
5
7
9
11
13
15
17
19
21
23
25
27
29
C GD
INPUT VOLTAGE (V)
R HI1
G
C DS
FIGURE 27. ALLOWED MAXIMUM GATE CHARGE vs INPUT
VOLTAGE
R LO1
UGATE
R G1
R GI1
C GS
Q1
To keep the IC within its operating temperature range, an
external power resistor could be used in series with the VIN pin to
S
PHASE
FIGURE 25. TYPICAL UPPER-GATE DRIVE TURN-ON PATH
PVCC
bring the heat out of the IC, or and external LDO could be used
when necessary.
Oscillator
The Oscillator is a sawtooth waveform, providing for leading edge
modulation with 350ns minimum PWM off-time. The oscillator
(Sawtooth) waveform has a DC offset of 1.0V. Each channel’s
peak-to-peak of the ramp amplitude is set proportional to the
R HI2
R LO2
LGATE
G
R G2
C GD
R GI2
C GS
D
C DS
Q2
voltage applied, which is corresponding the EN/VFF pin. See
Frequency Synchronization and Phase Lock
Loop
The FSYNC pin has two primary capabilities: fixed frequency
operation and synchronized frequency operation. By connecting a
GND
S
resistor (R FSYNC ) to GND from the FSYNC pin, the switching
frequency can be set at any frequency between 150kHz and
FIGURE 26. TYPICAL LOWER-GATE DRIVE TURN-ON PATH
33
1.5MHz. The value of R FSYNC can be estimated using Equation 16.
The frequency setting curve shown in Figure 28 is also provided to
assist in selecting the correct value for R FSYNC.
FN7892.1
August 16, 2012
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