参数资料
型号: ISL8130IRZ
厂商: Intersil
文件页数: 17/24页
文件大小: 0K
描述: IC REG CTRLR BST FLYBK PWM 20QFN
标准包装: 75
PWM 型: 电压模式
输出数: 1
频率 - 最大: 1.4MHz
占空比: 100%
电源电压: 4.5 V ~ 5.5 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 85°C
封装/外壳: 20-VFQFN 裸露焊盘
包装: 管件
ISL8130
ENSS
ISL8130
BOOT
C BOOT
PHASE
+5V
D 1
+VIN
Q 1
Q 2
L O
C O
V OUT
DV OSC
OSC
PWM
COMPARATOR
-
+
DRIVER
DRIVER
VIN
L O
PHASE
C O
ESR
V OUT
C SS
V CC
C VCC
V E/A
Z FB
(PARASITIC)
GND
FIGURE 30. PRINTED CIRCUIT BOARD SMALL SIGNAL LAYOUT
GUIDELINES
-
+
ERROR
AMP
Z IN
REFERENCE
All control traces, such as feedback resistor divider connection,
compensation network connection should be placed away from
DETAILED COMPENSATION COMPONENTS
the high dv/dt node. Use Kelvin sensing connection for current
sensing.
General PowerPAD Design Considerations
C 1
C 2
R 2
Z FB
C 3
Z IN
R 3
V OUT
Figure 31 is an example of how to use vias to remove heat from
the IC.
COMP
-
+
FB
R 4
R 1
V OUT = V REF x ? 1 + ------- ?
ISL8130
REF
? R 1 ?
? R 4 ?
FIGURE 32. VOLTAGE - MODE BUCK CONVERTER COMPENSATION
FIGURE 31. PCB VIA PATTERN
We recommend you fill the thermal pad area with vias. A typical
via array would be to fill the thermal pad footprint with space,
such that they are center on center 3x the radius apart from each
other. Keep the Vias small but not so small that their inside
DESIGN
This function is dominated by a DC Gain and the output filter (L O
and C O ), with a double pole break frequency at F LC and a zero at
F ESR . The DC Gain of the modulator is simply the input voltage
(V IN ) divided by the peak-to-peak oscillator voltage Δ V OSC .
F LC = ---------------------------------------
F ESR = ---------------------------------------------
diameter prevents solder wicking through the holes during
reflow.
Connect all vias to the ground plane. It is important the vias have
a low thermal resistance for efficient heat transfer. It is
important to have a complete connection of the plated
through-hole to each plane.
Modulator Break Frequency Equations
1
2 π ? L O ? C O
1
2 π ? ( ESR ? C O )
(EQ. 4)
(EQ. 5)
Feedback Compensation
Figure 32 highlights the voltage-mode control loop for a
synchronous-rectified buck converter. The output voltage (V OUT )
is regulated to the Reference voltage level. The error amplifier
(Error Amp) output (V E/A ) is compared with the oscillator (OSC)
triangular wave to provide a pulse-width modulated (PWM) wave
with an amplitude of VIN at the PHASE node. The PWM wave is
smoothed by the output filter (L O and C O ). The modulator transfer
function is the small-signal transfer function of V OUT /V E/A .
17
The compensation network consists of the error amplifier
(internal to the ISL8130) and the impedance networks Z IN and
Z FB . The goal of the compensation network is to provide a closed
loop transfer function with the highest 0dB crossing frequency
(f 0dB ) and adequate phase margin. Phase margin is the
difference between the closed loop phase at f 0dB and 180°. The
following equations relate to the compensation network’s poles,
zeros and gain to the components (R 1 , R 2 , R 3 , C 1 , C 2 , and C 3 ) in
Figure 32. Use the following guidelines for locating the poles and
zeros of the compensation network.
FN7954.3
October 5, 2012
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