参数资料
型号: ISL8130IRZ
厂商: Intersil
文件页数: 3/24页
文件大小: 0K
描述: IC REG CTRLR BST FLYBK PWM 20QFN
标准包装: 75
PWM 型: 电压模式
输出数: 1
频率 - 最大: 1.4MHz
占空比: 100%
电源电压: 4.5 V ~ 5.5 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 85°C
封装/外壳: 20-VFQFN 裸露焊盘
包装: 管件
ISL8130
Pin Descriptions (Continued)
PIN #
QFN, QSOP
9, 16
SYMBOL
RT
DESCRIPTION
This is the oscillator frequency selection pin. Connecting this pin directly to VCC5 will select the oscillator free running
frequency of 300kHz. By placing a resistor from this pin to GND, the oscillator frequency can be programmed from
100kHz to 1.4MHz. Figure 2 shows the oscillator frequency vs RT resistance.
1400
1300
1200
1100
1000
900
800
700
600
500
400
300
200
100
0
0
25
50
75
100
125
150
RT (k ? )
FIGURE 2. OSCILLATOR FREQUENCY vs RT
10, 17
11, 18
12, 19
13, 20
14, 1
15, 2
16, 3
17, 4
18, 5
19, 6
20, 7
21 (QSOP only)
FB
COMP
ENSS
PGOOD
CDEL
PGND
LGATE
PVCC
PHASE
UGATE
BOOT
EP
This pin is connected to the feedback resistor divider and provides the voltage feedback signal for the controller. This
pin sets the output voltage of the converter.
This pin is the error amplifier output pin. It is used as the compensation point for the PWM error amplifier.
This pin provides enable/disable function and soft-start for the PWM output. The output drivers are turned off when
this pin is held below 1V.
This pin provides a power-good status. It is an open collector output used to indicate the status of the output voltage.
The PGOOD signal can be delayed by a time proportional to a CDEL current of 2μA and the value of the capacitor
connected between this pin and ground. A 0.1μF will typically provide 125ms delay.
This pin provides the power ground for the IC. Tie this pin to the ground plane through the lowest impedance
connection.
This pin provides the PWM-controlled gate drive for the lower MOSFET in buck and buck/boost configuration.
This pin is the power connection for the gate drivers. Connect this pin to the VCC5 pin. Connect a minimum of 1.0μF
ceramic decoupling capacitor as close to the IC as possible at this pin.
This pin also provides a return path for the upper gate driver. In a buck configuration it is the junction point of the
inductor, the upper MOSFET source and the lower MOSFET drain. For boost, sepic and flyback configurations, this pin
is tied to the power ground.
This pin provides the PWM-controlled gate drive for the main switching MOSFET in all configurations.
This pin is used to generate level shifted gate drive signals on the UGATE pin. Connect this pin to the junction of the
bootstrap capacitor and the cathode of the bootstrap diode in a buck or buck/boost configuration. For other
topologies, connect this pin to PVCC. Please refer to typical application circuits beginning on page 5 for details.
This pad is electrically isolated. Connect this pad to the signal ground plane using at least five vias for a robust thermal
conduction path.
3
FN7954.3
October 5, 2012
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