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参数资料
| 型号： | ISL8200MEVAL1PHZ |
| 厂商： | Intersil |
| 文件页数： | 14/23页 |
| 文件大小： | 0K |
| 描述： | EVAL BAORD FOR ISL8200 |
| 产品培训模块： | Solutions for Industrial Control Applications |
| 标准包装： | 1 |
| 主要目的： | DC/DC，步降 |
| 输出及类型： | 1，非隔离 |
| 输出电压： | 0.6 ~ 6 V |
| 电流 - 输出： | 10A |
| 输入电压： | 3 ~ 20 V |
| 稳压器拓扑结构： | 降压 |
| 频率 - 开关： | 700kHz ~ 1.5MHz |
| 板类型： | 完全填充 |
| 已供物品： | 板 |
| 已用 IC / 零件： | ISL8200 |
ISL8200M
V OUT × t SW
V IN_MIN = ------------------------------------------
The output voltage accuracy can be improved by
maintaining the impedance at V OUTSET (internal
V SEN1+ ) at or below 1k Ω effective impedance. Note: the
impedance between V SEN1+ and V SEN1- is about 500k Ω .
The module has minimum input voltage at a given output
voltage, which needs to be a minimum of 1.43 times
output voltage if operating at F SW = 700kHz switching
frequency. This is due to the Minimum PWM OFF Time
(t MIN-OFF ).
The equation to determine the minimum V IN to support
the required V OUT is given by Equations 2 and 3:
(EQ. 2)
t SW – t MIN_OFF
t SW = switching period = 1/F SW
for the 700kHz switching frequency = 1428ns
be needed if further reduction of output ripple or dynamic
transient spike is required.
Functional Description
Initialization
The ISL8200M requires V CC and PVCC to be biased by a
single supply. Power-On Reset (POR) circuits
continually monitor the bias voltages (PVCC and V CC )
and the voltage at EN pin. The POR function initiates
soft-start operation 384 clock cycles after the EN pin
voltage is pulled to be above 0.8V, all input supplies
exceed their POR thresholds and the PLL locking time
expires. The enable pin can be used as a voltage
monitor and to set desired hysteresis with an internal
30μA sinking current going through an external
resistor divider. The sinking current is disengaged after
the system is enabled. This feature is especially
V IN_MIN = 1.43 × V OUT
(EQ. 3)
designed for applications that require higher input rail
POR for better undervoltage protection. For example,
Selection of the Input Capacitor
The input filter capacitor should be based on how much
ripple the supply can tolerate on the DC input line. The
larger the capacitor, the less ripple expected, but
consideration should be taken for the higher surge
current during power-up. The ISL8200M provides the
soft-start function that controls and limits the current
surge. The value of the input capacitor can be calculated
in 12V applications, R UP = 53.6k and R DOWN = 5.23k
will set the turn-on threshold (V EN_RTH ) to 10.6V and
turn-off threshold (V EN_FTH ) to 9V, with 1.6V
hysteresis (V EN_HYS ).
During shutdown or fault conditions, the soft-start is
quickly reset while UGATE and LGATE immediately
change state (<100ns) upon the input dropping below
POR.
C IN = -------------------
384
PVCC POR
CYCLES
by Equation 4:
I IN × Δ t
Δ V
Where:
C IN is the input capacitance (μF)
I IN is the input current (A)
Δ t is the turn on time of the high-side switch (μs)
(EQ. 4)
HIGH = ABOVE POR; LOW = BELOW POR
VCC POR SOFT-START
OF MODULE
AND
EN POR
PLL LOCKING
FIGURE 21. SOFT-START INITIALIZATION LOGIC
Δ V is the allowable peak-to-peak voltage (V)
In addition to the bulk capacitance, some low Equivalent
Series Inductance (ESL) ceramic capacitance is
recommended to decouple between the drain terminal of
the high side MOSFET and the source terminal of the low
side MOSFET. This is used to reduce the voltage ringing
created by the switching current across parasitic circuit
elements.
Output Capacitors
The ISL8200M is designed for low output voltage ripple.
The output voltage ripple and transient requirements can
be met with bulk output capacitors (C OUT ) with low
enough Equivalent Series Resistance (ESR). C OUT can be
a low ESR tantalum capacitor, a low ESR polymer
capacitor or a ceramic capacitor. The typical capacitance
is 330μF and decoupled ceramic output capacitors are
used per phase. The internally optimized loop
compensation provides sufficient stability margins for all
ceramic capacitor applications with a recommended total
value of 300μF per phase. Additional output filtering may
14
Voltage Feedforward
The voltage applied to the FF pin is fed to adjust the
sawtooth amplitude of the channel. The amplitude the
sawtooth is set to 1.25 times the corresponding FF
voltage when the module is enabled. This configuration
helps to maintain a constant gain
( G M = V IN ? D MAX ? Δ V RAMP ) and input voltage to achieve
optimum loop response over a wide input voltage range.
The sawtooth ramp offset voltage is 1V (equal to
0.8V*1.25), and the peak of the sawtooth is limited to
V CC - 1.4V. With V CC = 5.4V, the ramp has a maximum
peak-to-peak amplitude of V CC - 2.4V (equal to 3V); so
the feed-forward voltage effective range is typically 3x as
the ramp amplitude ranges from 1V to 3V.
A 384 cycle delay is added after the system reaches its
rising POR and prior to the soft-start. The RC timing at
the FF pin should be sufficiently small to ensure that the
input bus reaches its static state and the internal ramp
circuitry stabilizes before soft-start. A large RC could
cause the internal ramp amplitude not to synchronize
with the input bus voltage during output start-up or
FN6727.1
February 26, 2010
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| ISL8200MEVAL2PHZ | 功能描述:电源管理IC开发工具 ISL8200M EVAL BBRD 2 PHS 23LD ROH RoHS:否 制造商:Maxim Integrated 产品:Evaluation Kits 类型:Battery Management 工具用于评估:MAX17710GB 输入电压: 输出电压:1.8 V |
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