参数资料
型号: ISL8200MEVAL1PHZ
厂商: Intersil
文件页数: 5/23页
文件大小: 0K
描述: EVAL BAORD FOR ISL8200
产品培训模块: Solutions for Industrial Control Applications
标准包装: 1
主要目的: DC/DC,步降
输出及类型: 1,非隔离
输出电压: 0.6 ~ 6 V
电流 - 输出: 10A
输入电压: 3 ~ 20 V
稳压器拓扑结构: 降压
频率 - 开关: 700kHz ~ 1.5MHz
板类型: 完全填充
已供物品:
已用 IC / 零件: ISL8200
ISL8200M
Pin Descriptions (Continued)
PIN
NUMBER
21
22
23
PD1
PIN NAME
VCC
PGOOD
NC
Phase
PIN DESCRIPTION
Analog Input - This pin provides bias power for the analog circuitry. It’s operational range is 2.97V to
5.6V. In 3.3V applications, VCC, PVCC and VIN should be shorted to allow operation at the low end
input as it relates to the V CC falling threshold limit. This pin can be powered either by the internal linear
regulator or by an external voltage source.
Analog Output - Provides an open drain Power Good signal when the output is within 9% of nominal
output regulation point with 4% hysteresis (13%/9%), and soft-start is complete. PGOOD monitors the
outputs (VMON1) of the internal differential amplifiers. Output Voltage Range: 0V to V CC .
Not internal connected
Used for both the PHASE pin (Pin # 16) and for heat removal connecting to heat dissipation layers using
Thermal Pad Vias. Potential should be floating and not electrically connected to anything except PHASE pin 16.
PD2
V IN Thermal Used for both the PVIN pin (Pin # 17) and for heat removal connecting to heat dissipation layers using
Pad Vias. Potential should be floating and not electrically connected to anything except VPVIN pin 17.
PD3
PGND
Used for both the PGND pin (Pin # 18) and for heat removal connecting to heat dissipation layers using
Thermal Pad Vias. Potential should be floating and not electrically connected to anything except PGND pin 18.
PD4
V OUT Used for both the VOUT pin (Pin # 19) and for heat removal connecting to heat dissipation layers using
Thermal Pad Vias. Potential should be floating and not electrically connected to anything except VOUT pin 19.
Typical Application Circuits
VIN
U201
ISL8200M
PVIN
VOUT
VOUT
GND
R1
16.5k
CIN(CER)
VIN
2.2k
RSET
COUT
FF
GND
R2 CEN
4.12k 1nF
* Select R1 & R2
such that
0.8V<V EN <5.0V
ISF ETDRV1
EN
FSYNC_IN
CLKOUT
ISHARE_BUS
ISFETDRV
VOUT_SET
VSEN_REM-
PGOOD
PH_CNTRL
PGOOD1
(See Table 1,
V OUT - R SET on page 13)
VCC
CPVCC
10uF
RISHARE
5k
FIGURE 3. SINGLE PHASE 10A 1.2V OUTPUT CIRCUIT
5
FN6727.1
February 26, 2010
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