参数资料
型号: ISL8200MEVAL1PHZ
厂商: Intersil
文件页数: 18/23页
文件大小: 0K
描述: EVAL BAORD FOR ISL8200
产品培训模块: Solutions for Industrial Control Applications
标准包装: 1
主要目的: DC/DC,步降
输出及类型: 1,非隔离
输出电压: 0.6 ~ 6 V
电流 - 输出: 10A
输入电压: 3 ~ 20 V
稳压器拓扑结构: 降压
频率 - 开关: 700kHz ~ 1.5MHz
板类型: 完全填充
已供物品:
已用 IC / 零件: ISL8200
ISL8200M
1500
1400
1300
1200
1100
1000
900
800
Layout Guide
To achieve stable operation, low losses, and good
thermal performance some layout considerations are
necessary.
? The ground connection between PGND1 (pin 15) and
PGND (pin 18) should be a solid ground plane under
the module.
? Place a high frequency ceramic capacitor between
(1) PVIN and PGND (pin 18) and (2) a 10μF between
700
0
100
200
RFS-ext (k Ω )
300
400
PVCC and PGND1 (pin 15) as close to the module as
possible to minimize high frequency noise. High
frequency ceramic capacitors close to the module
FIGURE 27. RFS-ext vs SWITCHING FREQUENCY
By connecting the FSYNC_IN pin to an external square
pulse waveform (such as the CLKOUT signal, typically
50% duty cycle from another ISL8200M), the
ISL8200M will synchronize its switching frequency to
the fundamental frequency of the input waveform. The
maximum voltage to the FSYNC_IN pin is V CC + 0.3V.
The Frequency Synchronization feature will
synchronize the leading edge of the CLKOUT signal
with the falling edge of Channel 1’s PWM clock signal.
CLKOUT is not available until the PLL locks.
The locking time is typically 130μs for F SW = 500kHz.
EN is not released for a soft-start cycle until FSYNC is
stabilized and the PLL is in locking. It is recommended
to connect all EN pins together in multiphase
configuration.
The loss of a synchronization signal for 13 clock cycles
causes the IC to be disabled until the PLL returns
locking, at which point a soft-start cycle is initiated and
normal operation resumes. Holding FSYNC_IN low will
disable the IC.
Setting Relative Phase-Shift on CLKOUT
Depending upon the voltage level at PH_CNTRL, set by
the VCC resistor divider output, the ISL8200M operates
with CLKOUT phase shifted, as shown in Table 3. The
between VOUT and PGND will help to minimize noise
at the output ripple.
? Use large copper areas for power path (PVIN, PGND,
VOUT) to minimize conduction loss and thermal
stress. Also, use multiple vias to connect the power
planes in different layers.
? Keep the trace connection to the feedback resistor
short.
? Use remote sensed traces to the regulation point to
achieve a tight output voltage regulation, and keep
them in parallel. Route a trace from VSEN_REM- to a
location near the load ground, and a trace from
feedback resistor to the point-of-load where the tight
output voltage is desire.
? Avoid routing any sensitive signal traces, such as the
VOUT and VSENREM- sensing point near the PHASE
pin.
? FSYNC_IN is a sensitive pin. If it not use for
receiving external synchronization signal, then keep
the trace connecting to the pin short. A bypass
capacitor value 100pF connecting between
FSYNC_IN pin and GND1 can help to bypass the
noise sensitivity on the pin.
To
Load GND
phase shift is latched as V CC raises above POR so it
cannot be changed on the fly.
TABLE 3.
CEN
RFBT
To
VOUT
DECODING
PHASE for CLKOUT
REQUIRED
PH_CNTRL RANGE
<29% of V CC
29% to 45% of V CC
45% to 62% of V CC
62% to V CC
WRT CHANNEL 1
-60°
90°
120°
180°
PH_CNTRL
15% V CC
37% V CC
53% V CC
V CC
CPVCC
PV IN
CIN
COUT
PGND
V OUT
FIGURE 28. RECOMMENDED LAYOUT
18
FN6727.1
February 26, 2010
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