参数资料
| 型号： | ISL8500IRZ-T |
| 厂商： | Intersil |
| 文件页数： | 13/15页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK ADJ 2A 12DFN |
| 产品培训模块： | Solutions for Industrial Control Applications |
| 标准包装： | 6,000 |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 0.6 V ~ 19 V |
| 输入电压： | 4.5 V ~ 25 V |
| PWM 型： | 电压模式 |
| 频率 - 开关： | 500kHz |
| 电流 - 输出： | 2A |
| 同步整流器： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 12-VFDFN 裸露焊盘 |
| 包装： | 带卷 (TR) |
| 供应商设备封装： | 12-DFN（4x3） |
ISL8500
regard to the capacitor surge current rating. These
capacitors must be capable of handling the surge-current at
power-up. Some capacitor series available from reputable
zeros and gain to the components (R 1 , R 2 , R 3 , C 1 , C 2 , and
C 3 ) in Figure 22. Use the following guidelines for locating the
poles and zeros of the compensation network:
OSC
manufacturers are surge current tested.
DRIVER
PWM
COMPARATOR
V IN
L O
V DDQ
1. Pick Gain (R 2 /R 1 ) for desired converter bandwidth.
2. Place 1 ST Zero Below Filter’s Double Pole (~75% F LC ).
3. Place 2 ND Zero at Filter ’s Double Pole.
+
Δ V OSC
-
D
PHASE
C O
ESR
4. Place 1 ST Pole at the ESR Zero.
5. Place 2 ND Pole at Half the Switching Frequency.
Z FB
(PARASITIC)
6. Check Gain against Error Amplifier ’s Open-Loop Gain.
- Z IN
ERROR
V OUT
C 1
F Z1 = ------------------------------------
F P1 = ---------------------------------------------------------
2 π x R 2 x ? ---------------------- ?
1
F Z2 = -------------------------------------------------------
2 π x ( R 1 + R 3 ) x C 3
2 π x R 3 x C 3
V E/A
+
REFERENCE
AMP
DETAILED COMPENSATION COMPONENTS
Z FB
Z IN
C 2 R 2 C 3 R 3
7. Estimate Phase Margin - Repeat if Necessary.
Compensation Break Frequency Equations
1 1
2 π x R 2 x C 2 ? C 1 x C 2 ?
? C 1 + C 2 ?
1
F P2 = ------------------------------------
(EQ. 8)
COMP
-
+
FB
R 4
R 1
Figure 22 shows an asymptotic plot of the DC/DC
converter ’s gain vs frequency. The actual Modulator Gain
has a high gain peak due to the high Q factor of the output
ISL8500
REFERENCE
filter and is not shown in Figure 22. Using the previously
mentioned guidelines should give a Compensation Gain
FIGURE 21. VOLTAGE-MODE BUCK CONVERTER
COMPENSATION DESIGN AND OUTPUT
VOLTAGE SELECTION
Feedback Compensation
Figure 21 highlights the voltage-mode control loop for a
synchronous-rectified buck converter. The output voltage
(V OUT ) is regulated to the Reference voltage level. The error
amplifier output (V E/A ) is compared with the oscillator (OSC)
similar to the curve plotted. The open loop error amplifier
gain bounds the compensation gain. Check the
compensation gain at F P2 with the capabilities of the error
amplifier. The Closed Loop Gain is constructed on the graph
of Figure 4 by adding the Modulator Gain (in dB) to the
Compensation Gain (in dB). This is equivalent to multiplying
the modulator transfer function to the compensation transfer
function and plotting the gain.
triangular wave to provide a pulse-width modulated (PWM)
wave with an amplitude of V IN at the PHASE node. The
PWM wave is smoothed by the output filter (L O and C O ).
The modulator transfer function is the small-signal transfer
100
80
60
F Z1 F Z2
F P1
F P2
OPEN LOOP
ERROR AMP GAIN
function of V OUT /V E/A . This function is dominated by a DC
Gain and the output filter (L O and C O ), with a double pole
break frequency at F LC and a zero at F ESR . The DC Gain of
the modulator is simply the input voltage (V IN ) divided by the
peak-to-peak oscillator voltage Δ V OSC .
40
20
0
-20
20LOG
(R 2 /R 1 )
MODULATOR
GAIN
20LOG
(V IN / Δ V OSC )
COMPENSATION
GAIN
F LC = -------------------------------------------
F ESR = --------------------------------------------
F ESR
Modulator Break Frequency Equations
1 1
2 π x LO x CO 2 π x ESR x C O
(EQ. 7)
-40
-60
10
100
1k
F LC
10k 100k
FREQUENCY (Hz)
1M
CLOSED LOOP
GAIN
10M
The compensation network consists of the error amplifier
(internal to the ISL8500) and the impedance networks Z IN
and Z FB . The goal of the compensation network is to provide
a closed loop transfer function with the highest 0dB crossing
frequency (f 0dB ) and adequate phase margin. Phase margin
is the difference between the closed loop phase at f 0dB and
180°. Equation 8 relates the compensation network’s poles,
13
FIGURE 22. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
The compensation gain uses external impedance networks
Z FB and Z IN to provide a stable, high bandwidth (BW) overall
loop. A stable control loop has a gain crossing with
-20dB/decade slope and a phase margin greater than 45°.
Include worst case component variations when determining
phase margin.
FN6611.0
December 10, 2007
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