参数资料
| 型号： | ISL8500IRZ-T |
| 厂商： | Intersil |
| 文件页数： | 6/15页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK ADJ 2A 12DFN |
| 产品培训模块： | Solutions for Industrial Control Applications |
| 标准包装： | 6,000 |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 0.6 V ~ 19 V |
| 输入电压： | 4.5 V ~ 25 V |
| PWM 型： | 电压模式 |
| 频率 - 开关： | 500kHz |
| 电流 - 输出： | 2A |
| 同步整流器： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 12-VFDFN 裸露焊盘 |
| 包装： | 带卷 (TR) |
| 供应商设备封装： | 12-DFN（4x3） |
ISL8500
Pin Descriptions
FB (Pin 1) and COMP (Pin 2)
The standard buck regulator employs a single voltage
control loop. FB is the negative input to the voltage loop error
amplifier. COMP is the output of the error amplifier. The
output voltage is set by an external resistor divider
connected to FB. With a properly selected divider, the output
voltage can be set to any voltage between the power rail
(reduced by converter losses) and the 0.6V reference.
Connecting an AC network across COMP and FB provides
loop compensation to the amplifier.
In addition, the PWM regulator power good and
undervoltage protection circuitry use FB to monitor the
regulator output voltage.
SS (Pin 3)
Program pin for soft-start duration. A regulated 30μA pull-up
current source charges a capacitor connected from the pin to
GND. The output voltage of the converter follows the
ramping voltage on the SS pin.
EN (Pin 4)
PWM controller enable input. The PWM converter output is
held off when the pin is pulled to ground. When the voltage
on this pin rises above 1.7V, the chip is enabled.
PG (Pin 5)
PWM converter power good output. Open drain logic output
that is pulled to ground when the output voltage is outside
regulation limits. Connect a 100k Ω resistor from this pin to
VDD. Pin is low when the buck regulator output voltage is
not within 10% of the respective nominal voltage, or during
the soft-start interval. Pin is high impedance when the output
is within regulation.
GND (Pin 6)
Ground connect for the IC and thermal relief for the package.
The exposed pad must be connected to GND and soldered
to the PCB. All voltage levels are measured with respect to
this pin.
VDD (Pin 7)
Internal 5V linear regulator output provides bias to all the
internal control logic. The ISL8500 may be powered directly
from a 5V (±10%) supply at this pin. When used as a 5V supply
input, this pin must be externally connected to VIN. The VDD
pin must always be decoupled to GND with a ceramic bypass
capacitor (minimum 1μF) located close to the pin.
TABLE 1. INPUT SUPPLY CONFIGURATION
BOOT (Pin 8)
Floating bootstrap supply pin for the power MOSFET gate
driver. The bootstrap capacitor provides the necessary
charge to turn and hold on the internal N-Channel MOSFET.
Connect an external capacitor from this pin to PHASE.
PHASE (Pins 9, 10)
Switch node connections to internal power MOSFET source,
external output inductor and external diode cathode.
VIN (Pins 11, 12)
The input supply for the PWM regulator power stage and the
source for the internal linear regulator that provides bias for
the IC. Place a ceramic capacitor from VIN to GND, close to
the IC for decoupling (typical 10μF).
INPUT
5.5V to 25V
5V ±10%
PIN CONFIGURATION
Connect the input supply to the VIN pin only. The
VDD pin will provide a 5V output from the internal
linear regulator.
Connect the input supply to the VIN and VDD pins.
6
FN6611.0
December 10, 2007
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