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| 型号： | ISL8501EVAL1Z |
| 厂商： | Intersil |
| 文件页数： | 14/19页 |
| 文件大小： | 0K |
| 描述： | EVALUATION BOARD FOR ISL8501 |
| 标准包装： | 1 |
| 主要目的： | DC/DC，LDO 步降 |
| 输出及类型： | 3，非隔离 |
| 输出电压： | 3.3V，1.2V，1.8V |
| 电流 - 输出： | 1A，500mA，500mA |
| 输入电压： | 4.5 ~ 25 V |
| 稳压器拓扑结构： | 降压 |
| 频率 - 开关： | 500kHz |
| 板类型： | 完全填充 |
| 已供物品： | 板 |
| 已用 IC / 零件： | ISL8501 |
ISL8501
charges the external soft-start capacitor. The voltage on SS
begins ramping linearly from ground until the voltage across
the soft-start capacitor reaches 3.0V. This linear ramp is
applied to the non-inverting input of the internal error
R1
V OUT
amplifier and overrides the nominal 0.6V reference. The
output voltage reaches its regulation value when the soft-
start capacitor voltage reaches 1.6V. Connect a capacitor
from SS pin to ground. This capacitor, along with an internal
30 μ A current source sets the soft-start interval of the
EA
0.6V
REFERENCE
R2
converter, t SS .
FIGURE 31. EXTERNAL RESISTOR DIVIDER
C SS [ μ F ] = 50 ? t SS [ S ]
(EQ. 1)
The buck output can be program as high as 20V. Proper
heatsinking must be provided to insure that the junction
R1 ? 0.6V
Upon disable, SS pin voltage will discharge to zero voltage.
Power Good
PG_PWM is an open-drain output of a window comparator
that continuously monitors the buck regulator output voltage.
PG_PWM is actively held low when EN is low and during the
buck regulator soft-start period. After the soft-start period
terminates, PG_PWM becomes high impedance as long as
the output voltage is within ±10% of the nominal regulation
voltage set by FB_PWM. When VOUT drops 10% below or
rises 10% above the nominal regulation voltage, the
ISL8501 pulls PG_PWM low. Any fault condition forces
PG_PWM low until the fault condition is cleared by attempts
to soft-start. For logic level output voltages, connect an
external pull-up resistor between PG_PWM and VCC. A
100k resistor works well in most applications. Note that the
PG_PWM window detector is completely independent of the
undervoltage protection fault detectors and the state of
LDO1 and LDO2 outputs.
PG_LDO is an open drain pull-down NMOS output that will
sink 1mA at 0.3V max. PG_LDO monitors both LDO1 and
LDO2 output. It goes to the active low state if either LDO
output is below regulation by a value greater than 15%.
When the one of the LDO is disabled, the PG_LDO switch to
only monitor the active LDO output.
Output Voltage Selection
All three regulator output voltages can be programmed using
external resistor dividers that scale the voltage feedback
relative to the internal reference voltage. The scaled voltage
is fed back to the inverting input of the error amplifier. Refer
to Figure 3.
The output voltage programming resistor, R 2 , will depend on
the value chosen for the feedback resistor, R 1 , and the
desired output voltage, V OUT , of the regulator. See Equation 1.
The value for the feedback resistor is typically between 1k Ω
and 10k Ω .
R2 = ---------------------------------- (EQ. 2)
V OUT – 0.6V
If the output voltage desired is 0.6V, then R 2 is left
unpopulated.
14
temperature do not exceed +125°C.
When the output is set greater than 3.6V, it is recommended
to pre-load at least 1mA and make sure that the input rise
time is >> faster than the VOUT1 rise time. This allows the
BOOT capacitor adequate time to charge for proper
operation.
Protection Features
The ISL8501 limits current in all on-chip power devices to
limit on-chip power dissipation. Overcurrent limits on all three
regulators protect internal power devices from excessive
thermal damage. Undervoltage protection circuitry on the
buck regulator provides a second layer of protection for the
internal power device under high current conditions.
Buck Regulator Overcurrent Protection
During the PWM on-time, the current through the internal
switching MOSFET is sampled and scaled through an
internal pilot device. The sampled current is compared to a
nominal 2A overcurrent limit. If the sampled current exceeds
the overcurrent limit reference level, an internal overcurrent
fault counter is set to 1 and an internal flag is set. The
internal power MOSFET is immediately turned off and will
not be turned on again until the next switching cycle.
The protection circuitry continues to monitor the current and
turns off the internal MOSFET as described. If the over-
current condition persists for four sequential clock cycles,
the over-current fault counter overflows indicating an
overcurrent fault condition exists. The regulator is shut down
and power good goes low. If the overcurrent condition clears
prior to the counter reaching four consecutive cycles, the
internal flag and counter are reset.
The protection circuitry attempts to recover from the
overcurrent condition after waiting 4 soft-start cycles. The
internal overcurrent flag and counter are reset. A normal
soft-start cycle is attempted and normal operation continues
if the fault condition has cleared. If the overcurrent fault
counter overflows during soft-start, the converter shuts down
and this hiccup mode operation repeats.
FN6500.1
July 12, 2007
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