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参数资料
| 型号： | ISL8501EVAL1Z |
| 厂商： | Intersil |
| 文件页数： | 7/19页 |
| 文件大小： | 0K |
| 描述： | EVALUATION BOARD FOR ISL8501 |
| 标准包装： | 1 |
| 主要目的： | DC/DC，LDO 步降 |
| 输出及类型： | 3，非隔离 |
| 输出电压： | 3.3V，1.2V，1.8V |
| 电流 - 输出： | 1A，500mA，500mA |
| 输入电压： | 4.5 ~ 25 V |
| 稳压器拓扑结构： | 降压 |
| 频率 - 开关： | 500kHz |
| 板类型： | 完全填充 |
| 已供物品： | 板 |
| 已用 IC / 零件： | ISL8501 |
ISL8501
Pin Descriptions
VIN
The input supply for the PWM regulator power stage and the
source for the internal linear regulator that provides bias for
the IC. Place a ceramic capacitor from VIN to GND, close to
the IC for decoupling (typical 1 μ F).
PVCC
Connect this pin to VCC.
GND
Ground connect for the IC and thermal relief for the package.
The exposed pad must be connected to GND and soldered
to the PCB. All voltage levels are measured with respect to
this pin.
VCC
Internal 5V linear regulator output provides bias to all the
internal control logic. The ISL8501 may be powered directly
from a 5V (±10%) supply at this pin. When used as a 5V
supply input, this pin must be externally connected to VIN.
The VCC pin must always be decoupled to GND with a
ceramic bypass capacitor (minimum 1 μ F) located close to
the pin.
TABLE 1. INPUT SUPPLY CONFIGURATION
EN
PWM controller enable input. The PWM converter and
LDO's outputs are held off when the pin is pulled to ground.
When the voltage on this pin rises above 1.7V, the chip is
enabled.
SS
Program pin for soft-start duration. A regulated 30 μ A pull-up
current source charges a capacitor connected from the pin to
GND. The output voltage of the converter follows the
ramping voltage on the SS pin.
VIN_LDO1, VIN_LDO2
Input voltage pin for each LDO.
VOUT1, VOUT2
LDO output pins. Bypass with a minimum of 2.2 μ F, low ESR
capacitor to GND for stable operation.
FB_LDO1, FB_LDO2
Used to set the output of LDO with the proper selection of
resistor divider. The resistors should be selected to provide a
minimum current of 200nA load for the LDO.
CC1, CC2
Compensation capacitor connection for each LDO. Connect
a 0.033 μ F capacitor from each pin to ground.
INPUT
6V to 25V
5V ±10%
PIN CONFIGURATION
Connect the input supply to the VIN pin only. The
VCC pin will provide a 5V output from the internal
linear regulator.
Connect the input supply to the VIN and VCC pins.
EN_LDO1, EN_LDO2
These pins are threshold-sensitive enable inputs for the
individual LDOs. Held low, this pin disables the respective
LDO.
PG_PWM
FB and COMP
The standard buck regulator employs a single voltage
control loop. FB is the negative input to the voltage loop error
amplifier. COMP is the output of the error amplifier. The
output voltage is set by an external resistor divider
connected to FB. With a properly selected divider, the output
voltage can be set to any voltage between the power rail
(reduced by converter losses) and the 0.6V reference.
Connecting an AC network across COMP and FB provide
loop compensation to the amplifier.
In addition, the PWM regulator power good and under-
voltage protection circuitry use FB to monitor the regulator
output voltage.
PHASE
Switch node connections to internal power MOSFET source,
external output inductor, and external diode cathode.
BOOT
Floating bootstrap supply pin for the power MOSFET gate
driver. The bootstrap capacitor provides the necessary
charge to turn and hold on the internal N-Channel MOSFET.
Connect an external capacitor from this pin to PHASE.
7
PWM converter power good output. Open drain logic output
that is pulled to ground when the output voltage is outside
regulation limits. Connect a 100k Ω resistor from this pin to
VCC. Pin is low when the buck regulator output voltage is
not within 10% of the respective nominal voltage, or during
the soft-start interval. Pin is high impedance when the output
is within regulation.
PG_LDO
Combined LDO power good output. Connect a 100k Ω
resistor from this pin to VCC.
FN6500.1
July 12, 2007
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