参数资料
| 型号： | ISL8502IRZ |
| 厂商： | Intersil |
| 文件页数： | 12/19页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK SYNC ADJ 2.5A 24QFN |
| 标准包装： | 75 |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 0.6 V ~ 14 V |
| 输入电压： | 5V，5.5 V ~ 14 V |
| PWM 型： | 电压模式 |
| 频率 - 开关： | 500kHz ~ 1.2MHz |
| 电流 - 输出： | 2.5A |
| 同步整流器： | 是 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-VFQFN 裸露焊盘 |
| 包装： | 管件 |
| 供应商设备封装： | 24-QFN（4x4） |
ISL8502
Typical Performance Curves
V IN = 12V, V OUT = 2.5V, I O = 2A, fs = 500kHz, L = 4.7μH, C IN = 20μF, C OUT = 100μF + 22μF,
T A = +25° C, unless otherwise noted. (Continued)
PHASE1
10V/DIV
VOUT1
1V/DIV
IL1
1A/DIV
PGOOD1
5V/DIV
FIGURE 31. RECOVER FROM POSITIVE SHORT CIRCUIT
Functional Pin Descriptions
PGOOD (Pin 1)
PGOOD is an open drain output that will pull to low if the
output goes out of regulation or a fault is detected. PGOOD
is equipped with a fixed delay upon output power-up. The
delay is approximately 250ms at switching frequency
500kHz and 108ms at 1.2MHz.
SGND (Pin 2)
PHASE1
5V/DIV
VOUT1 RIPPLE
50mV/DIV
IL1
2A/DIV
IOUT1
2A/DIV
FIGURE 32. LOAD TRANSIENT
As a master or a stand alone device, tie this pin directly to
the VCC pin. Do not short M/S pin to GND.
FS (Pin 6)
This pin provides oscillator switching frequency adjustment.
By placing a resistor (R T ) from this pin to GND, the switching
frequency can be programmed as desired between 500kHz
and 1.2MHz as shown in Equation 1.
R T [ k Ω ] = ------------------------------
The SGND terminal of the ISL8502 provides the return path
for the control and monitor portions of the IC.
48000
f OSC [ kHz ]
(EQ. 1)
EN (Pin 3)
The Enable pin is a bi-directional pin. If the voltage on this pin
exceeds the enable threshold voltage, the part is enabled. If a
fault is detected, the EN pin will be pulled low via internal
circuitry for a duration of 4 soft-start periods. For automatic
start-up, use 10k Ω to 100k Ω pull-up resistor connecting to
VCC.
SYNCH (Pin 4)
This is a bi-directional pin that is used to synchronize slave
devices to the Master device. As a Master device, this pin
outputs the clock signal to which the slave devices
synchronize. As a slave device, this pin is an input to receive
the clock signal from the master device.
If configured as a slave device, the ISL8502 will be disabled
if there is no clock signal from the master device on the
SYNCH pin.
Leave this pin unconnected if the IC is used in stand alone
operation.
M/S (Pin 5)
As a slave device, tie a 5k Ω resistor between this pin and
Tying the FS pin to the VCC pin will force the switching
frequency to 800kHz.
Using resistors with values below 40k Ω (1.2MHz) or with
values higher than 97k Ω (500kHz) may damage the
ISL8502.
COMP (Pin 7) and FB (Pin 8)
The switching regulator employs a single voltage control
loop. FB is the negative input to the voltage loop error
amplifier. The output voltage is set by an external resistor
divider connected to FB. With a properly selected divider, the
output voltage can be set to any voltage between the power
rail (reduced by converter losses) and the 0.6V reference.
Loop compensation is achieved by connecting an AC
network across COMP and FB.
The FB pin is also monitored for undervoltage events.
SS (Pin 9)
Connect a capacitor from this pin to ground. This capacitor,
along with an internal 30μA current source, sets the soft-start
interval of the converter, t SS as shown in Equation 2.
ground.
12
C SS [ μ F ] = 50 ? t SS [ S ]
(EQ. 2)
FN6389.2
June 29, 2010
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