参数资料
| 型号： | ISL8502IRZ |
| 厂商： | Intersil |
| 文件页数： | 16/19页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK SYNC ADJ 2.5A 24QFN |
| 标准包装： | 75 |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 0.6 V ~ 14 V |
| 输入电压： | 5V，5.5 V ~ 14 V |
| PWM 型： | 电压模式 |
| 频率 - 开关： | 500kHz ~ 1.2MHz |
| 电流 - 输出： | 2.5A |
| 同步整流器： | 是 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-VFQFN 裸露焊盘 |
| 包装： | 管件 |
| 供应商设备封装： | 24-QFN（4x4） |
ISL8502
a voltage rating of 1.5x is a conservative guideline. For most
cases, the RMS current rating requirement for the input
capacitor of a buck regulator is approximately 1/2 the DC
OSC
PWM
COMPARATOR
DRIVER
V IN
L O
V OUT
load current.
The maximum RMS current through the input capacitors
Δ V OSC
-
+
DRIVER
PHASE
C O
may be closely approximated using Equation 10:
ESR
-------------- × ? I OUT
× ? 1 – -------------- ? + ------ × ? ----------------------------- × -------------- ? ?
V IN ?
L × f OSC
V IN ? ?
?
V OUT ?
V IN ?
MAX
2
? 12
V OUT 1 ? V IN – V OUT V OUT ? 2 ?
(EQ. 10)
Z FB
V E/A
-
+
ERROR
Z IN
REFERENCE
(PARASITIC)
For a through-hole design, several electrolytic capacitors
may be needed. For surface mount designs, solid tantalum
AMP
DETAILED COMPENSATION COMPONENTS
capacitors can be used, but caution must be exercised with
regard to the capacitor surge current rating. These
capacitors must be capable of handling the surge-current at
power-up. Some capacitor series available from reputable
C 2
C 1
R 2
Z FB
C 3
Z IN
R 3
V OUT
manufacturers are surge current tested.
Feedback Compensation
Figure 34 highlights the voltage-mode control loop for a
synchronous-rectified buck converter. The output voltage
COMP
-
+
FB
R 4
R 1
V OUT = 0.6 × ? 1 + ------ 1 - ?
(V OUT ) is regulated to the Reference voltage level. The error
amplifier output (V E/A ) is compared with the oscillator (OSC)
triangular wave to provide a pulse-width modulated (PWM)
wave with an amplitude of V IN at the PHASE node. The
PWM wave is smoothed by the output filter (L O and C O ).
The modulator transfer function is the small-signal transfer
function of V OUT /V E/A . This function is dominated by a DC
Gain and the output filter (L O and C O ), with a double pole
break frequency at F LC and a zero at F ESR . The DC Gain of
ISL8502
REFERENCE
? R ?
? R 4 ?
FIGURE 34. VOLTAGE-MODE BUCK CONVERTER
COMPENSATION DESIGN AND OUTPUT
VOLTAGE SELECTION
Modulator Break Frequency Equations
f LC = -------------------------------------------
f ESR = --------------------------------------------
the modulator is simply the input voltage (V IN ) divided by the
peak-to-peak oscillator voltage DV OSC . The ISL8502
incorporates a feed forward loop that accounts for changes
1
2 π x LO x CO
1
2 π x ESR x C O
(EQ. 11)
in the input voltage. This maintains a constant modulator
gain.
16
The compensation network consists of the error amplifier
(internal to the ISL8502) and the impedance networks Z IN
and Z FB . The goal of the compensation network is to provide
a closed loop transfer function with the highest 0dB crossing
frequency (f 0dB ) and adequate phase margin. Phase margin
is the difference between the closed loop phase at f 0dB and
180°. Equation 12 relates the compensation network’s poles,
zeros and gain to the components (R 1 , R 2 , R 3 , C 1 , C 2 and
C 3 ) in Figure 34. Use these guidelines for locating the poles
and zeros of the compensation network:
1. Pick Gain (R 2 /R 1 ) for desired converter bandwidth.
2. Place 1 st Zero Below Filter’s Double Pole (~75% F LC ).
3. Place 2 nd Zero at Filter ’s Double Pole.
4. Place 1 st Pole at the ESR Zero.
5. Place 2 nd Pole at Half the Switching Frequency.
6. Check Gain against Error Amplifier ’s Open-Loop Gain.
7. Estimate Phase Margin - Repeat if Necessary.
FN6389.2
June 29, 2010
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