参数资料
| 型号： | ISL8502IRZ |
| 厂商： | Intersil |
| 文件页数： | 15/19页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK SYNC ADJ 2.5A 24QFN |
| 标准包装： | 75 |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 0.6 V ~ 14 V |
| 输入电压： | 5V，5.5 V ~ 14 V |
| PWM 型： | 电压模式 |
| 频率 - 开关： | 500kHz ~ 1.2MHz |
| 电流 - 输出： | 2.5A |
| 同步整流器： | 是 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-VFQFN 裸露焊盘 |
| 包装： | 管件 |
| 供应商设备封装： | 24-QFN（4x4） |
ISL8502
After the initial spike, attributable to the ESR and ESL of the
capacitors, the output voltage experiences sag. This sag is a
direct consequence of the amount of capacitance on the output.
During the removal of the same output load, the energy stored
in the inductor is dumped into the output capacitors. This
energy dumping creates a temporary hump in the output
voltage. This hump, as with the sag, can be attributed to the
Output Inductor Selection
The output inductor is selected to meet the output voltage
ripple requirements and minimize the converter ’s response
time to the load transient. The inductor value determines the
converter ’s ripple current and the ripple voltage is a function
of the ripple current. The ripple voltage and current are
approximated by using Equation 8:
total amount of capacitance on the output. Figure 33 shows a
typical response to a load transient.
Δ I =
V IN - V OUT
Fs x L
x
V OUT
V IN
Δ V OUT = Δ I x ESR
(EQ. 8)
The amplitudes of the different types of voltage excursions
can be approximated using Equation 5.
Increasing the value of inductance reduces the ripple current
Δ V ESL = ESL ? ---------------
Δ V ESR = ESR ? I tran
dI tran
dt
and voltage. However, the large inductance values reduce
the converter ’s response time to a load transient.
L out ? I tran
Δ V SAG = --------------------------------------------------
2
C out ? ( V in – V out )
One of the parameters limiting the converter ’s response to
a load transient is the time required to change the inductor
L out ? I tran
Δ V HUMP = --------------------------------
2
C out ? V out
(EQ. 5)
current. Given a sufficiently fast control loop design, the
ISL8502 will provide either 0% or 100% duty cycle in
response to a load transient. The response time is the time
required to slew the inductor current from an initial current
--------------------------------- + ESR ? I tran
Number of Capacitors = -----------------------------------------------------------------------
where: I tran = Output Load Current Transient and C out = Total
Output Capacitance
In a typical converter design, the ESR of the output capacitor
bank dominates the transient response. The ESR and the
ESL are typically the major contributing factors in
determining the output capacitance. The number of output
capacitors can be determined by using Equation 6, which
relates the ESR and ESL of the capacitors to the transient
load step and the voltage limit (DVo):
ESL ? dI tran
dt
Δ V o
(EQ. 6)
If DV SAG and/or DV HUMP are found to be too large for the
output voltage limits, then the amount of capacitance may
need to be increased. In this situation, a trade-off between
output inductance and output capacitance may be
necessary.
The ESL of the capacitors, which is an important parameter
in the previous equations, is not usually listed in databooks.
Practically, it can be approximated using Equation 7 if an
Impedance vs Frequency curve is given for a specific
capacitor:
value to the transient current level. During this interval the
difference between the inductor current and the transient
current level must be supplied by the output capacitor.
Minimizing the response time can minimize the output
capacitance required.
The response time to a transient is different for the
application of load and the removal of load. Equation 9 gives
the approximate response time interval for application and
removal of a transient load:
L x I TRAN L x I TRAN
t RISE = t FALL =
V IN - V OUT V OUT
(EQ. 9)
where: I TRAN is the transient load current step, t RISE is the
response time to the application of load, and t FALL is the
response time to the removal of load. The worst case
response time can be either at the application or removal of
load. Be sure to check both of these equations at the
minimum and maximum output levels for the worst case
response time.
Input Capacitor Selection
Use a mix of input bypass capacitors to control the voltage
overshoot across the MOSFETs. Use small ceramic
capacitors for high frequency decoupling and bulk capacitors
to supply the current needed each time the upper MOSFET
ESL = ----------------------------------------
C ( 2 ? π ? f res )
1
2
(EQ. 7)
turns on. Place the small ceramic capacitors physically close
to the MOSFETs and between the drain of the upper
where: f res is the frequency where the lowest impedance is
achieved (resonant frequency).
The ESL of the capacitors becomes a concern when
designing circuits that supply power to loads with high rates
of change in the current.
15
MOSFET and the source of the lower MOSFET.
The important parameters for the bulk input capacitance are
the voltage rating and the RMS current rating. For reliable
operation, select bulk capacitors with voltage and current
ratings above the maximum input voltage and largest RMS
current required by the circuit. Their voltage rating should be
at least 1.25x greater than the maximum input voltage, while
FN6389.2
June 29, 2010
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