参数资料
| 型号： | ISL8502IRZ |
| 厂商： | Intersil |
| 文件页数： | 17/19页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK SYNC ADJ 2.5A 24QFN |
| 标准包装： | 75 |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 0.6 V ~ 14 V |
| 输入电压： | 5V，5.5 V ~ 14 V |
| PWM 型： | 电压模式 |
| 频率 - 开关： | 500kHz ~ 1.2MHz |
| 电流 - 输出： | 2.5A |
| 同步整流器： | 是 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-VFQFN 裸露焊盘 |
| 包装： | 管件 |
| 供应商设备封装： | 24-QFN（4x4） |
ISL8502
100
80
60
f Z1 f Z2
f P1
f P2
OPEN LOOP
ERROR AMP GAIN
As an example, consider the turn-off transition of the control
MOSFET. Prior to turn-off, the MOSFET is carrying the full
load current. During turn-off, current stops flowing in the
MOSFET and is picked up by the lower MOSFET. Any
40
20
0
-20
-40
-60
20LOG
(R 2 /R 1 )
MODULATOR
GAIN
10 100
1k
f LC
10k
20LOG
(V IN / Δ V OSC )
f ESR
100k 1M
COMPENSATION
GAIN
CLOSED LOOP
GAIN
10M
parasitic inductance in the switched current path generates a
large voltage spike during the switching interval. Careful
component selection, tight layout of the critical components,
and short, wide traces minimizes the magnitude of voltage
spikes.
There are two sets of critical components in the ISL8502
switching converter. The switching components are the most
FREQUENCY (Hz)
FIGURE 35. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
Compensation Break Frequency Equations
critical because they switch large amounts of energy, and
therefore tend to generate large amounts of noise. Next, are
the small signal components, which connect to sensitive
nodes or supply critical bypass current and signal coupling.
f Z1 = ------------------------------------
f Z2 = -------------------------------------------------------
f P1 = ---------------------------------------------------------
2 π x R 2 x ? ---------------------- ?
f P2 = ------------------------------------
1
2 π x R 2 x C 1
1
2 π x ( R 1 + R 3 ) x C 3
1
? C 1 x C 2 ?
? C 1 + C 2 ?
1
2 π x R 3 x C 3
A multi-layer printed circuit board is recommended. Figure 36
shows the connections of the critical components in the
converter. Note that capacitors C IN and C OUT could each
represent numerous physical capacitors. Dedicate one solid
layer (usually a middle layer of the PC board) for a ground
plane and make all critical component ground connections
(EQ. 12)
Figure 35 shows an asymptotic plot of the DC/DC
converter ’s gain vs frequency. The actual Modulator Gain
has a high gain peak due to the high Q factor of the output
filter and is not shown in Figure 35. Using the guidelines
provided should give a Compensation Gain similar to the
curve plotted. The open loop error amplifier gain bounds the
compensation gain. Check the compensation gain at F P2
with the capabilities of the error amplifier. The Closed Loop
Gain is constructed on the graph of Figure 35 by adding the
Modulator Gain (in dB) to the Compensation Gain (in dB).
This is equivalent to multiplying the modulator transfer
function to the compensation transfer function and plotting
the gain.
The compensation gain uses external impedance networks
Z FB and Z IN to provide a stable, high bandwidth (BW) overall
loop. A stable control loop has a gain crossing with
-20dB/decade slope and a phase margin greater than +45°.
Include worst case component variations when determining
phase margin. A more detailed explanation of voltage mode
control of a buck regulator can be found in Tech Brief TB417,
entitled “Designing Stable Compensation Networks for
Single Phase Voltage Mode Buck Regulators.”
Layout Considerations
Layout is very important in high frequency switching
converter design. With power devices switching efficiently
between 500kHz and 1.2MHz, the resulting current
transitions from one device to another cause voltage spikes
across the interconnecting impedances and parasitic circuit
elements. These voltage spikes can degrade efficiency,
radiate noise into the circuit, and lead to device overvoltage
stress. Careful component layout and printed circuit board
design minimizes these voltage spikes.
17
with vias to this layer. Dedicate another solid layer as a
power plane and break this plane into smaller islands of
common voltage levels. Keep the metal runs from the
PHASE terminals to the output inductor short. The power
plane should support the input power and output power
nodes. Use copper filled polygons on the top and bottom
circuit layers for the phase nodes. Use the remaining printed
circuit layers for small signal wiring. The wiring traces from
the GATE pins to the MOSFET gates should be kept short
and wide enough to easily handle the 1A of drive current.
In order to dissipate heat generated by the internal V TT
LDO, the ground pad, pin 29, should be connected to the
internal ground plane through at least five vias. This allows
the heat to move away from the IC and also ties the pad to
the ground plane through a low impedance path.
The switching components should be placed close to the
ISL8502 first. Minimize the length of the connections
between the input capacitors, C IN , and the power switches
by placing them nearby. Position both the ceramic and bulk
input capacitors as close to the upper MOSFET drain as
possible. Position the output inductor and output capacitors
between the upper and lower MOSFETs and the load. Make
the PGND and the output capacitors as short as possible.
The critical small signal components include any bypass
capacitors, feedback components, and compensation
components. Place the PWM converter compensation
components close to the FB and COMP pins. The feedback
resistors should be located as close as possible to the FB
pin with vias tied straight to the ground plane as required.
FN6389.2
June 29, 2010
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