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参数资料
| 型号： | ISL89367FRTAZ-T |
| 厂商： | Intersil |
| 文件页数： | 5/14页 |
| 文件大小： | 0K |
| 描述： | IC MOSFET DRIVER 2CH 6A 16TDFN |
| 标准包装： | 4,000 |
| 配置： | 低端 |
| 输入类型： | 与和反相 |
| 延迟时间： | 25ns |
| 配置数： | 2 |
| 输出数： | 2 |
| 电源电压： | 4.5 V ~ 16 V |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-WFDFN 裸露焊盘 |
| 供应商设备封装： | 16-TDFN |
| 包装： | 带卷 (TR) |
ISL89367
DC Electrical Specifications V DD = 12V, GND = 0V, No load on OUTA or OUTB, RDELA = RDELB = FDELA = FDELB = 0k ? unless
otherwise specified. Boldface limits apply over the operating junction temperature range, -40°C to +125°C. (Continued)
T J = +25°C
T J = -40°C to +125°C
MIN
MAX
MIN
MAX
PARAMETERS
SYMBOL
TEST CONDITIONS
(Note 9)
TYP
(Note 9)
(Note 9)
(Note 9)
UNITS
INPUTS
Input Range for
IN1A, IN2A, IN1B, IN2B
Input Range for INVA, INVB
Logic 0 Threshold for IN1A,
IN2A, IN1B, IN2B
Logic 1 Threshold for IN1A,
IN2A, IN1B, IN2B
Logic 0 Threshold for INVA,
INVB
Logic 1 Threshold for INVA,
INVB
Input Capacitance of IN1A,
IN2A, IN1B, 1N2B, INVA, INVB
Input Bias Current for
IN1A, IN2A, IN1B, IN2B
Input Bias Current for
INVA, INVB
V IN
V INV
V IL
V IH
V ILV
V IHV
C IN
I IN
I INV
V IN is referenced to V REF-
V INV is referenced to V SS
Nominally 37% x ((V REF+ ) - (V REF- ))
Nominally 63% x ((V REF+ ) - (V REF- ))
V ILV is referenced to V SS
V IHV is referenced to V SS
V REF- < V IN < V REF+
V SS < V INV < V DD
-
-
-
-
-
-
-
-
-
-
-
37
63
0.9
1.5
2
-
-
-
-
-
-
-
-
-
-
-
Vref-
V SS
34
60
1
1.5
-
-10
-40
Vref+
V DD
40
66
1.2
1.7
-
+10
+40
V
V
%
%
V
V
pF
μA
μA
OUTPUTS
High Level Output Voltage
Low Level Output Voltage
V OHA V OHB
V OLA
V OLB
-
-
-
-
-
-
V DD - 0.1
GND
V DD
GND + 0.1
V
V
Peak Output Source Current
Peak Output Sink Current
I O
I O
V O (initial) = 0V, C LOAD = 10nF
V O (initial) = 12V, C LOAD = 10nF
-
-
-6
+6
-
-
-
-
-
-
A
A
NOTES:
9. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
10. This parameter is taken from the simulation models for the input FET. The actual capacitance on this input will be dominated by the PCB parasitic
capacitance.
11. A 400μs delay further inhibits the release of the output state when the UV positive going threshold is crossed. See Figure 9.
12. The true state of a specific part number is defined by the input logic symbol.
AC Electrical Specifications V DD = 12V, GND = 0V, No Load on OUTA or OUTB, RDELA = RDELB = FDELA = FDELB = 0k ? unless
otherwise specified. Boldface limits apply over the operating junction temperature range, -40°C to +125°C.
T J = +25°C
T J = -40°C
to +125°C
TEST CONDITIONS
MIN
MAX
MIN
MAX
PARAMETERS
Output Rise Time (see Figure 4)
Output Fall Time (see Figure 4)
Output Rising Edge Propagation Delay (see Figure 3)
SYMBOL
t R
t F
t RDLYA,
t RDLYB
/NOTES
C LOAD = 10nF,
10% to 90%
C LOAD = 10nF,
90% to 10%
(Note 9)
-
-
-
TYP
20
20
25
(Note 9)
-
-
-
(Note 9)
-
-
-
(Note 9)
40
40
50
UNITS
ns
ns
ns
5
FN7727.1
October 8, 2012
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