参数资料
型号: ISL9112IRT7Z-T7A
厂商: Intersil
文件页数: 12/20页
文件大小: 0K
描述: IC REG BUCK BOOST SYNC 5V 12TDFN
标准包装: 1
类型: 降压(降压),升压(升压)
输出类型: 固定
输出数: 1
输出电压: 5V
输入电压: 1.8 V ~ 5.5 V
PWM 型: 电压模式
频率 - 开关: 2.5MHz
电流 - 输出: 1.2A
同步整流器:
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 12-WFDFN 裸露焊盘
包装: 标准包装
供应商设备封装: 12-TDFN-EP(3x3)
其它名称: ISL9112IRT7Z-T7ADKR
ISL9110, ISL9112
Functional Description
Functional Overview
Refer to the “Block Diagram” on page 2. The ISL9110, ISL9112
implements a complete buck boost switching regulator, with
PWM controller, internal switches, references, protection
circuitry, and control inputs.
The PWM controller automatically switches between buck and
boost modes as necessary to maintain a steady output voltage,
with changing input voltages and dynamic external loads.
The ISL9110 provides output-power-good and input-power-good
open-drain status outputs on pins 7 and 8. In the ISL9112, these
pins are used for an I 2 C interface, allowing programmable output
voltage and access to the ultrasonic mode and slew rate limit
control bits.
Internal Supply and References
Referring to the “Block Diagram” on page 2, the ISL9110,
ISL9112 provides two power input pins. The PVIN pin supplies
input power to the DC/DC converter, while the VIN pin provides
operating voltage source required for stable V REF generation.
Separate ground pins (GND and PGND) are provided to avoid
problems caused by ground shift due to the high switching
currents.
Enable Input
A master enable pin EN allows the device to be enabled. Driving
EN low invokes a power-down mode, where most internal device
functions, including input and output power good detection, are
disabled.
Soft Discharge
When the device is disabled by driving EN low, an internal resistor
between VOUT and GND is activated. This internal resistor has
typical 120 ? resistance.
POR Sequence and Soft-start
Bringing the EN pin high allows the device to power-up. A number
of events occur during the start-up sequence. The internal voltage
reference powers up, and stabilizes. The device then starts
operating. There is a typical 1ms delay between assertion of the
EN pin and the start of switching regulator soft-start ramp.
The soft-start feature minimizes output voltage overshoot and
input inrush currents. During soft-start, the reference voltage is
ramped to provide a ramping V OUT voltage. While output voltage
is lower than approximately 20% of the target output voltage,
switching frequency is reduced to a fraction of the normal
switching frequency to aid in producing low duty cycles necessary
to avoid input inrush current spikes. Once the output voltage
exceeds 20% of the target voltage, switching frequency is
increased to its nominal value.
When the target output voltage is higher than the input voltage,
there will be a transition from buck mode to boost mode during
the soft-start sequence. At the time of this transition, the ramp
rate of the reference voltage is decreased, such that the output
voltage slew rate is decreased. This provides a slower output
voltage slew rate.
12
The V OUT ramp time is not constant for all operating conditions.
Soft-start into boost mode will take longer than soft-start into
buck mode. The total soft-start time into buck operating mode is
typically 2ms, whereas the typical soft-start time into boost
mode operating mode is typically 3ms. Increasing the load
current will increase these typical soft-start times.
Overcurrent Protection
When the current in the P-Channel MOSFET is sensed to reach
the current limit for 16 consecutive switching cycles, the internal
protection circuit is triggered, and switching is stopped for
approximately 20ms. The device then performs a soft-start cycle.
If the external output overcurrent condition exists after the
soft-start cycle, the device will again detect 16 consecutive
switching cycles reaching the peak current threshold. The
process will repeat as long as the external overcurrent condition
is present. This behavior is called ‘hiccup mode’.
Short Circuit Protection
The ISL9110, ISL9112 provides short-circuit protection by
monitoring the feedback voltage. When feedback voltage is
sensed to be lower than a certain threshold, the PWM oscillator
frequency is reduced in order to protect the device from damage.
The P-Channel MOSFET peak current limit remains active during
this state.
Undervoltage Lockout
The undervoltage lockout (UVLO) feature prevents abnormal
operation in the event that the supply voltage is too low to
guarantee proper operation. When the VIN voltage falls below the
UVLO threshold, the regulator is disabled.
PG Status Output (ISL9110 only)
An open drain output-power-good signal is provided in the
ISL9110. An internal window comparator is used to detect when
VOUT is significantly higher or lower than the target output
voltage. The PG output will be driven low when sensed VOUT
voltage is outside of this ‘power good’ window. When VOUT
voltage is inside the ‘power good’ window, the PG pin goes Hi-Z.
The PG detection circuit detects this condition by monitoring
voltage on the FB pin. Hysteresis is provided for the upper and
lower PG thresholds to avoid oscillation of the PG output.
BAT Status Output (ISL9110 only)
The ISL9110 provides an open drain input-power-good status
output. The BAT status pin will be driven low when VIN rises
above the VT BMON threshold. The BAT status output goes Hi-Z
when V BAT falls below the VT BMON threshold. Hysteresis is
provided for the VT BMON threshold to avoid oscillation of the BAT
output.
Ultrasonic Mode (ISL9112 only)
The ISL9112 provides an ultrasonic mode that can be enabled
through I 2 C control by setting the ULTRA bit in the control register.
In ultrasonic mode, the PFM switching frequency is forced to be
above the audio frequency range.
This ultrasonic mode applies only to PFM mode operation. With
the ULTRA bit set to ‘1’, PFM mode switching frequency is forced
FN7649.2
July 13, 2012
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